An instruction fetch policy handling L2 cache misses in SMT processors

Proceedings - Eighth International Conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005

Volumn 2005, Issue , 2005, Pages 519-525

  Sun, Caixia ^a   Tang, Hongwei ^a   Zhang, Minxuan ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

HARMONIC ANALYSIS; PROGRAM PROCESSORS; PUBLIC POLICY;

INSTRUCTION FETCH POLICY HANDLING; MULTIPLE FETCH PRIORITIES; SIMULTANEOUS MULTITHREADING (SMT) PROCESSORS;

CACHE MEMORY;

EID: 33847145063     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCASIA.2005.22     Document Type: Conference Paper

References (12)

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