Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

Microelectronics Reliability

Volumn 47, Issue 2-3, 2007, Pages 196-204

  Lee, Chang Chun ^a   Lee, Chien Chen ^a   Ku, Hsiao Tung ^a   Chang, Shu Ming ^a   Chiang, Kuo Ning ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRONIC EQUIPMENT; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; RELIABILITY THEORY; SILICON WAFERS; SOLDERED JOINTS;

ANALYSIS OF VARIANCE (ANOVA); DUMMY SOLDER JOINTS; GEOMETRICAL DESIGN PARAMETERS; RAMBUS DRAM LAYOUT;

CHIP SCALE PACKAGES;

EID: 33846650937     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2006.09.004     Document Type: Article

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