On enhancing eutectic solder joint reliability using a second-reflow-process approach

IEEE Transactions on Advanced Packaging

Volumn 23, Issue 1, 2000, Pages 9-14

  Chiang, Kuo Ning ^a,b   Lin, Yung Te ^a   Cheng, Hsien Chie ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b NATIONAL CENTER FOR HIGH PERFORMANCE COMPUTING   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CONTACT ANGLE; FLIP CHIP DEVICES; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; RELIABILITY; SOLDERED JOINTS;

BALL GRID ARRAY (BGA); SOLDER REFLOW;

ELECTRONICS PACKAGING;

EID: 0033907410     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.826755     Document Type: Article

References (11)

1. K. N. Chiang and W. L. Chen Electronic packaging reflow shape prediction for the solder mask defined ball grid array," ASM E Trans. J. Electron. Packag., vol. 120, pp. 175-178, June 1998.
2. S. K. Patra, S. S. Sritharan, and Y. C. Lee Quantitative characterization of a flip-chip solder joint," J. Appl. Mech., vol. 62, pp. 390-397, 1995.
3. S. M. Heinrich, P. E. Liedtke, N. J. Nigro, A. F. Elkouh, and P. S. Lee Effect of chip and pad geometry on solder joint formation in SMT," J. Electron. Packag., vol. 115, pp. 43339, 1993.
4. P. E. Liedtke Prediction of solder joint geometry in surface mount technology-An analytical approach," Ph.D. dissertation, Marquette Univ., Milwaukee, WI, 1993.
5. K. A. Brakke, Surface Evolver Manual. Minneapolis, MN: The Geometry Center, 1994.
6. S. M. Heinrich, M. Schaefer, S. A. Schroeder, and P. S. Lee Prediction of solder joint geometries in array-type interconnects," ASME J. Electron. Packag., vol. 118, pp. 114-121, 1996.
7. R. J. Klein Wassink, Soldering in Electronics, 2nd ed. Ayr, Scotland: Electrochem.l Publ. Ltd., 1989.
8. B. M. Guenin, R. C. Marrs, and R. J. Molnar Analysis of a thermally enhanced ball grid array package," IEEE Trans. Comp., Packag., Manufact. Technol. A, vol. 18, pp. 749-757, Dec. 1995.
9. H. C. Cheng, K. N. Chiang, and M. H. Lee An effective approach for three-dimensional finite element analysis of ball grid array typed packages," ASME Trans. J. Electron. Packag., vol. 120, pp. 129-134, 1998.
10. Y. H. Pao, E. Jih, V. Siddapureddy, X. Song, and R. Liu A thermal fatigue model for surface mount leadless chip resistor (LCR) solder joints," Sens., Model., Sitnul. Eng. Electron. Packag., EEP, vol. 17, pp. 1-12, 1996.
11. H. L. Lau, Ball Grid Array Technology, New York: McGraw Hill, 1995, ch. 13.