Design issues in CMOS differential LC oscillators

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 5, 1999, Pages 717-724

  Hajimiri, Ali ^a   Lee, Thomas H ^b  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT MEASUREMENT; ELECTRIC INDUCTORS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; PHASE LOCKED LOOPS; SIGNAL NOISE MEASUREMENT; VOLTAGE DISTRIBUTION MEASUREMENT;

DIFFERENTIAL INDUCTOR-CAPACITOR OSCILLATORS;

OSCILLATORS (ELECTRONIC);

EID: 0032635507     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.760384     Document Type: Article

References (8)

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3. J. Craninckx, M. Steyaert, and H. Miyakawa, "A fully integrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800 systems," in Proc. CICC, May 1997, pp. 403-406.
4. T. I. Ahrens, A. Hajimiri, and T. H. Lee, "A 1.6 GHz, 0.5 mW CMOS LC low phase noise VCO using bond wire inductance," in Proc. 1st Int. Workshop Design of the Mixed-Mode Integrated Circuits and Applications, Cancun, Mexico, July 1997, pp. 69-71.
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6. T. I. Ahrens and T. H. Lee, "A 1.4 GHz 3 mW CMOS LC low phase noise VCO using tapped bond wire inductance," in Proc. ISLPED, Aug. 1998, pp. 16-19.
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8. A. A. Abidi, "High-frequency noise measurements of FET's with small dimensions," IEEE Trans. Electron Devices, vol. ED-33, pp. 1801-1805, Nov. 1986.