Copper die bumps (first level interconnect) and low-k dielectrics in 65nm high volume manufacturing

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 1611-1615

  Yeoh, Andrew ^a   Chang, Margherita ^a   Pelto, Christopher ^a   Huang, Tzuen Luh ^a   Balakrishnan, Sridhar ^a   Leatherman, Gerald ^a   Agraharam, Sairam ^a   Wang, Guotao ^a   Wang, Zhiyong ^a   Chiang, Daniel ^a   Stover, Patrick ^a   Brandenburger, Peter ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; CRACKS; DIELECTRIC MATERIALS; ELECTRIC RESISTANCE; FAILURE ANALYSIS; PASSIVATION;

COPPER DIE BUMPS; DIE FAILURE; INTEL (CO); INTERLAYER DIELECTRICS (ILD'S);

FLIP CHIP DEVICES;

EID: 33845567569     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645872     Document Type: Conference Paper

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