Using mobilize power management IP for dynamic & static power reduction in SoC at 130 nm

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn 2005, Issue , 2005, Pages 240-246

  Hillman, Dan ^a  

^a Virtual Silicon ^*

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC BATTERIES; INTERNET; MICROPROCESSOR CHIPS; MOBILE COMPUTING; NETWORK PROTOCOLS; SEMICONDUCTING SILICON;

MOBILIZE POWER MANAGEMENT; POWERSAVER STANDARD CELLS; VOLTAGE ISLAND; VOLTAGE SCALING;

ENERGY MANAGEMENT;

EID: 33646939836     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.324     Document Type: Conference Paper

References (3)

1. Each configuration of the extensible, configurable Xtensa processor is created by the Xtensa Processor Generator from a unique designer-defined specification of both predefined configuration options and designer-defined instruction extensions. The generator can create a wide range of processor cores, including small task engines, high performance DSPs, media processors and network processors all sharing the common base Xtensa instruction set architecture. The configuration used in this paper has the minimum set of configuration options and includes only the base ISA elements without custom instruction extensions. The power minimization techniques discussed can be applied equally to any Xtensa processor configuration.
2. Peters, E., Taglieri, G., & Vemury, L. (2000). Low Power Synthesis Flow For a Configurable Core. Boston: SNUG.
3. International Technology Roadmap for Semiconductors, System Drivers. (2001). (p. 17).