An offset-cancelled CMOS clock-recovery/demux with a half-rate linear phase detector for 2.5Gb/s optical communication

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 74-75+434

  Larsson, P ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITANCE; CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; JITTER; PHASE COMPARATORS; PHASE LOCKED LOOPS; TRANSCEIVERS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK-RECOVERY CIRCUITS; PHASE DETECTORS (PD);

TIMING CIRCUITS;

EID: 0035054796     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 3GHz 32dB CMOS limiting amplifier for SONET OC-48 receivers
2. A monolithic 480Mb/s parallel AGC/decision/clock recovery circuit in 1.2μm CMOS
3. 700-Mb/s/pin CMOS signalling interface using current integrating receivers
4. Clock recovery from random binary signals
5. A 90mW 4Gb/s equalized I/O circuit with input offset cancellation
6. A CMOS self-calibrating frequency synthesizer