40 Gb/s integrated clock and data recovery circuit in a silicon bipolar technology

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn , Issue , 1998, Pages 136-139

  Wurzer, M ^a   Boeck, J ^a   Zirwas, W ^a   Knapp, H ^a   Schumann, F ^a   Felder, A ^a   Treitinger, L ^a  

^a SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LIGHT TRANSMISSION; PHASE LOCKED LOOPS; POLYCRYSTALLINE MATERIALS; SEMICONDUCTING SILICON;

INTEGRATED CLOCK AND DATA RECOVERY CIRCUITS (CDR); POLYSILICON BIPOLAR TECHNOLOGY;

BIPOLAR INTEGRATED CIRCUITS;

EID: 0032312708     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)