Tri-Scan: A novel DFT technique for CMOS path delay fault testing

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 1118-1127

  Datta, Ramyanshu ^a   Gupta, Ravi ^a   Sebastine, Antony ^a   Abraham, Jacob A ^a   D'Abreu, Manuel ^b  

^a The University of Texas at Austin   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATED TESTING EQUIPMENT (ATE); COMPUTATION COSTS; PATH DELAY FAULT TESTING; TIMING VERIFICATION;

CMOS INTEGRATED CIRCUITS; CROSSTALK; DELAY CIRCUITS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; MICROPROCESSOR CHIPS; OBSERVABILITY; THERMAL NOISE; VLSI CIRCUITS;

DESIGN FOR TESTABILITY;

EID: 18144421242     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. K.-T. Cheng, S. Devadas, and K. Keutzer. Delay-Fault Test Generation and Synthesis for Testability under a Standard Scan Design Methodology. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 12(8):1217-1231, August 1993.
2. R. Datta, J. A. Abraham, R. Montoye, W. Belluomini, C. Mcdowell, H. Ngo, J. Kuang, and K. Nowka. A Low Latency Low Power 4-to-2 Carry Save Adder. In International Symposium on Circuits and Systems.
3. B. Dervisoglu and G. Strong. Design for Testability: Using ScanPath Techniques for Path-Delay Test and Measurement. In International Test Conference, pages 365-374. IEEE, October 1991.
4. S. Devadas and K. Keutzer. Validatable Non-Robust Delay-Fault-Testable Circuits via Logic Synthesis. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 11(12):1559-1573, December 1992.
5. E. B. Eichelberger and T. W. Williams. A Logic Design Structure for Design for Testability. In Design Automation Conference, pages 462-468. ACM, June 1977.
6. S. Hesley and et. al. A 7th-Generation x86 Microprocessor. In International Solid State Circuits Conference, pages 92-93. IEEE, February 1999.
7. E. Hsieh, R. Rasmussen, L. Vidunas, and W. Davis. Delay Test Generation. In Design Automation Conference, pages 486-491. ACM, June 1977.
8. J. P. Lesser and J. J. Shedletsky. An Experimental Delay Test Generator for LSI Logic. IEEE Transactions on Computers, 29(3):235-248, March 1980.
9. Y. Levendel and P. Menon. Transition Faults in Combinational Circuits: Input Transition Test Generation and Fault Simulation . In International Fault Tolerant Computing Symposium, pages 278-283. IEEE, July 1986.
10. C. J. Lin and S. M. Reddy. On Delay Fault Testing in Logic Circuits. IEEE Transactions on Computer Aided Design, 6(5):694-703, September 1987.
11. M.Hansen, H. Yalcin, and J. Hayes. Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering. IEEE Design and Test of Computers, 16(3):72-80, July-September 1999.
12. J. Savir. Skewed Load transition Test: Part I, Calculus. In International Test Conference, pages 705-713. IEEE, Sepetember 1992.
13. J. Savir. Skewed Load transition Test: Part II, Coverage. In International Test Conference, pages 714-722. IEEE, Sepetember 1992.
14. J. Savir. On Broad-Side Delay test. In VLSI Test Symposium, pages 284-290. IEEE, April 1994.
15. N. A. Touba and E. J. McCluskey. Applying Two Pattern Tests usign Scan-Mapping. In VLSI Test Symposium, pages 393-397. IEEE, May 1996.
16. University of Texas at Austin. EE382M VLSI-2 Class Notes "http:/www.ece.utexas.edu/mcdermot".
17. T. J. Wood. The Test and Debug Features of the AMD-K7™ Microprocessor. In International Test Conference, pages 130-136. IEEE, April 1999.