Timing driven gate duplication: Complexity issues and algorithms

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2000-January, Issue , 2000, Pages 447-450

  Srivastava, Ankur ^a   Kastner, Ryan ^a   Sarrafzadeh, Majid ^a  

^a Northwestern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; DYNAMIC PROGRAMMING; LOGIC SYNTHESIS; POLYNOMIALS; CAPACITANCE; ELECTRIC NETWORK TOPOLOGY; HEURISTIC METHODS; OPTIMIZATION; THEOREM PROVING;

DELAY IMPROVEMENTS; DELAY OPTIMIZATION; LOCAL OPTIMIZATIONS; PERFORMANCE OPTIMIZATIONS; PERFORMANCE-DRIVEN; RESEARCH COMMUNITIES; TECHNOLOGY INDEPENDENT; TIMING OPTIMIZATION;

OPTIMIZATION; COMPUTATIONAL COMPLEXITY;

DELAY OPTIMIZATION; TIMING DRIVEN GATE DUPLICATION;

EID: 0034477856     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2000.896512     Document Type: Conference Paper

References (9)

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