Using logic duplication to improve performance in FPGAs

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 136-142

  Schabas, Karl ^a   Brown, Stephen D ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

FPGA; Logic duplication

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; CRITICAL PATH ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; SHIFT REGISTERS; TABLE LOOKUP;

BASIC LOGIC ELEMENTS; LOGIC DUPLICATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038349130     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611835.611838     Document Type: Conference Paper

References (11)

1. Altera. "Stratix Datasheets", Available from: http://www.altera.com/products/devices/stratix/stx-index.jsp
2. Betz V. Architecture and CAD for Speed and Area Optimization of FPGAs. Ph. D. Dissertation. University of Toronto, 1998.
3. Betz, V., and Rose, J. VPR: A New Packing, Placement and Routing tool for FPGA research. Int. Workshop on Field-Programmable Logic and Applications, 1997, pp. 213-222.
4. Betz, V., Rose, J., and Marquardt A. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
5. Cheng C. RISA: Accurate and Efficient Placement Routability Modeling. ICCAD, 1994, pp. 690-695.
6. Cong, J. and Ding, Y. FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. IEEE Trans. On Computer-Aided Design, Jan. 1994, pp. 1-12.
7. Kirkpatrick, S., Gelatt, C., and Vecchi M. Optimization by Simulated Annealing. Science, May 13, 1983, pp. 671-680.
8. Marquardt, A., Betz, V., and Rose, J. Using Cluster-Based Logic blocks and Timing-Driven Packing to Improve FPGA Speed and Density. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 1999, pp. 37-46.
9. Schabas, K. M.A.Sc. Thesis in Progress: Using Logic Duplication to Improve Performance in FPGAs. University of Toronto, 2002.
10. Sentovich, E. M., et al. SIS: A System for Sequential Circuit Analysis. Tech. Report No. UCB/ERL M92/41, University of California, Berkeley, 1992.
11. Singh, A. and Marek-Sadowska, M. Efficient Circuit Clustering for Area and Power Reduction in FPGAs. International Symposium on Field Programmable Gate arrays, Monterey, CA, February 2002, pp 59-66.