Analyzing statistical timing behavior of coupled interconnects using quadratic delay change characteristics

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2003-January, Issue , 2003, Pages 183-188

  Chen, Tom ^a,b   Hajjar, Amjad ^b  

^a HEWLETT PACKARD COMPANY   (United States)

^b Veterinary Dentistry and Oral Surgery   (United States)

Author keywords

CMOS process; Coupling circuits; Delay effects; Design methodology; Integrated circuit interconnections; Signal analysis; Timing; Uncertainty; Very large scale integration; Wires

Indexed keywords

CMOS INTEGRATED CIRCUITS; COUPLED CIRCUITS; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; SIGNAL ANALYSIS; TIMING CIRCUITS; UNCERTAINTY ANALYSIS; VLSI CIRCUITS; WIRE;

CMOS PROCESSS; DELAY EFFECTS; DESIGN METHODOLOGY; INTEGRATED CIRCUIT INTERCONNECTIONS; TIMING; UNCERTAINTY;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33750904071     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2003.1194729     Document Type: Conference Paper

References (12)

1. S.R. Nassif, "Design for variability in DSM technologies", IEEE Proc. 1st Int. Symp. on Quality Electronic Design (ISQED), pp.451-454, San Jose, CA, March, 2000.
2. D. Boning and J. Chung, "Statistical metrology: understanding spatial vairation in semiconductor manufacturing", Proc. of the SPIE, pp.16-26, Dec. 1996.
3. D. Boning and J. Chung, "Statistical metrology - measurement and modeling of variation for advanced process development and design rule generation", Proc. of Int. Conf. on Characterization and Metrology for ULSI Technology, pp.395-404, March, 1998.
4. D. Boning et. al., "Spatial variation in semiconductor process: Modeling for control", Proc. of 2nd Int. Symp. on Process Control, Diagnostics, and Modeling in Semiconductor Manufacturing, pp.72-83, May, 1997.
5. C. Nicoletta et al., "A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect," IEEE Journal Solid State Circuits, v. 34, n. 11, pp. 1478-1491, 1999
6. R. Senthinathan, et. al., "A 650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video," IEEE Journal Solid State Circuits, v. 34, n. 11, pp. 1454-1465, 1999
7. A. Gattiker et. al., "Timing yield estimation from static timing analysis", Proc. of 2nd Int. Symp. on Quality Electronic Design, pp.437-442, March, 2001.
8. V. Mehrotra et. al., "A Methodology for modelling the effects of systematic within-die interconnect and device variation on circuit performance", 37th Design Automation Conf., pp.172-175, June, 2000.
9. W. Dai and J. Hao, "Timing analysis taking into account interconnect process variation", 6th Int. Workshop on Statistical Metrology, pp.51-53, June, 2001.
10. T. Sato, et. al., "Characterization of interconnect coupling noise using In-situ delay-change curve measurements," Proc. IEEE 13th Int. ASCI/SOC Conf., pp. 321-325, 2000
11. F. Dartu, L. Pileggi, "Calculating worst-case gate delays due to dominant capacitance coupling," 34th Design Automation conference, pp. 46-51, 1997
12. K. Agarwal, et. al., "Efficient generation of delay change curves for noise-aware timing analysis," IEEE 15th Int. Conf. on VLSI Design, 2002