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Volumn , Issue , 2002, Pages 77-84

Efficient generation of delay change curves for noise-aware static timing analysis

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN;

EID: 84962260194     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2002.994889     Document Type: Conference Paper
Times cited : (22)

References (12)
  • 1
    • 0033698637 scopus 로고    scopus 로고
    • On switch factor based analysis of coupled RC interconnects
    • A. B. Kahng, S. Muddu, and E. Sarto, "On switch factor based analysis of coupled RC interconnects," Proc. DAC, pp. 79-84, 2000.
    • (2000) Proc. DAC , pp. 79-84
    • Kahng, A.B.1    Muddu, S.2    Sarto, E.3
  • 2
    • 0030686019 scopus 로고    scopus 로고
    • Calculating worst-case gate delays due to dominant capacitive coupling
    • F. Dartu and L. T. Pileggi, "Calculating worst-case gate delays due to dominant capacitive coupling," Proc. DAC, pp. 46-51, 1997.
    • (1997) Proc. DAC , pp. 46-51
    • Dartu, F.1    Pileggi, L.T.2
  • 4
    • 0003107721 scopus 로고    scopus 로고
    • Deep submicron static timing analysis in presence of crosstalk
    • P. F. Tehrani, S. W. Chyou, and U. Ekambaram, "Deep submicron static timing analysis in presence of crosstalk," Proc. ISQED, pp. 505-512, 2000.
    • (2000) Proc. ISQED , pp. 505-512
    • Tehrani, P.F.1    Chyou, S.W.2    Ekambaram, U.3
  • 6
    • 0033681236 scopus 로고    scopus 로고
    • Characterization of interconnect coupling noise using in-situ delay-change curve measurements
    • T. Sato, Y. Cao, D. Sylvester, and C. Hu, "Characterization of interconnect coupling noise using in-situ delay-change curve measurements," International ASIC/SoC Conference, pp.321-325, 2000.
    • (2000) International ASIC/SoC Conference , pp. 321-325
    • Sato, T.1    Cao, Y.2    Sylvester, D.3    Hu, C.4
  • 8
    • 0027222295 scopus 로고
    • Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's
    • Jan
    • T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's", IEEE Trans. on Electron Devices, pp. 118-125, Jan. 1993.
    • (1993) IEEE Trans. on Electron Devices , pp. 118-125
    • Sakurai, T.1
  • 9
    • 0033683026 scopus 로고    scopus 로고
    • Multi-aggressor relative window method for timing analysis including crosstalk delay degradation
    • Y. Sasaki and K. Yano, "Multi-aggressor relative window method for timing analysis including crosstalk delay degradation," Proc. CICC, pp. 495-498, 2000.
    • (2000) Proc. CICC , pp. 495-498
    • Sasaki, Y.1    Yano, K.2
  • 10
    • 84949743939 scopus 로고    scopus 로고
    • Improved crosstalk modeling for noise constrained interconnect optimization
    • J. Cong, D. Z. Pan, and P. V. Srinivas, "Improved crosstalk modeling for noise constrained interconnect optimization," ASP-DAC, 2001
    • (2001) ASP-DAC
    • Cong, J.1    Pan, D.Z.2    Srinivas, P.V.3
  • 11
    • 0028756124 scopus 로고
    • Modeling the 'effective capacitance' for the RC interconnect of CMOS gates
    • Dec
    • J. Qian, S. Pullela, and L. T. Pillage, "Modeling the 'effective capacitance' for the RC interconnect of CMOS gates," IEEE Trans. Computer-Aided Design, pp. 1526-1535, Dec.1994.
    • (1994) IEEE Trans. Computer-Aided Design , pp. 1526-1535
    • Qian, J.1    Pullela, S.2    Pillage, L.T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.