650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 11, 1999, Pages 1454-1465

  Senthinathan, Ramesh ^a   Fischer, Stephen ^a   Rangchi, Hamid ^a   Yazdanmehr, Hadi ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA REDUCTION; DECODING; ELECTRONICS PACKAGING; FLIP FLOP CIRCUITS; IMAGE CODING; INTERCONNECTION NETWORKS; MULTIMEDIA SYSTEMS; STANDARDS; THREE DIMENSIONAL COMPUTER GRAPHICS; TIMING CIRCUITS;

DATA STREAMING; DELAY-LOCKED LOOPS (DLL); ON-DIE-CLOCK (ODC) SHRINK/STRETCH CIRCUITS; SINGLE INSTRUCTION MULTIPLE DATA (SIMD);

MICROPROCESSOR CHIPS;

EID: 0033221549     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.799850     Document Type: Article

References (9)

1. K. Diefendorff, "Pentium® III = Pentium® II + SSE," MicroDesign Resources, Microprocessor Rep., vol. 13, no. 3, p. 6, Mar. 1999.
2. J. Schutz and R. Wallace, "A 450 MHz IA 32 P6 family microprocessor," in ISSCC Dig. Tech. Papers, Feb. 1998, pp. 236-237.
3. L. Gwennap, "P6 underscores Intel's lead," MicroDesign Resources, Microprocessor Rep., vol. 9, no. 2, p. 6, Feb. 1995.
4. M. Kagan, S. Gochman, D. Orenstien, and D. Lin, "MMX™ microarchitecture of Pentium® processors with MMX™ technology and Pentium® II microprocessors," Intel Technol. J., vol. Q3, 1997.
5. R. Senthinathan, A. C. Cangellaris, and J. L. Prince, "Reference plane parasitics modeling and their contribution to the power and ground path "Effective" inductance as seen by the output drivers," IEEE Trans. Microwave Theory Tech., vol. 42, p. 1765, Sept. 1994.
6. G. Geannopoulous and X. Dai, "An adaptive digital deskewing circuit for clock distribution networks," in ISSCC Dig. Tech. Papers, Feb. 1998, pp. 400-401.
7. M. Haycock and R. Mooney, "A 2.5 Gb/s bi-directional signaling technology," in Proc. Hot Interconnects Symp. V, Aug. 1997, pp. 149-156.
8. G. Taylor, T. Arabi, K. Hose, J. Jones, S. Kim, R. Kuppuswamy, R. Mooney, J. Price, and A. Sarangi, "A 2 MB, 3.6 GB/s back-side-bus cache for an IA 32450 MHz microprocessor," in 1998 Symp. VLSI Circuits Dig. Tech. Papers, 1998, p. 184.
9. R. Senthinathan and J. L. Prince, "Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise," IEEE J. Solid-State Circuits, vol. 28, p. 1383, Dec. 1993.