Design criteria for low noise front-end electronics in the 0.13 μm CMOS generation

Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

Volumn 568, Issue 1, 2006, Pages 343-349

  Re, Valerio ^a,c   Manghisoni, Massimo ^a,c   Ratti, Lodovico ^b,c   Speziali, Valeria ^b,c   Traversi, Gianluca ^a,c  

^a UNIVERSITY OF BERGAMO   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

^c INFN SEZIONE DI PAVIA   (Italy)

Author keywords

CMOS; Device scaling; Front end; Noise; Readout electronics

Indexed keywords

ACOUSTIC NOISE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; NOISE ABATEMENT; PARAMETER ESTIMATION;

DEVICE SCALING; FRONT END ELECTRONICS; NOISE LIMITS; READOUT ELECTRONICS;

READOUT SYSTEMS;

EID: 33750309772     PISSN: 01689002     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.nima.2006.06.003     Document Type: Article

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