Systolic designs for DCT using a low-complexity concurrent convolutional formulation

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 16, Issue 9, 2006, Pages 1041-1050

  Meher, Pramod Kumar ^a,b  

^a IEEE   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Digital signal processing chip; Discrete cosine transform (DCT); Systolic array; Very large scale integration (VLSI)

Indexed keywords

DIGITAL SIGNAL PROCESSING CHIP; DISCRETE COSINE TRANSFORM (DCT); SYSTOLIC ARRAY;

ALGORITHMS; ARRAYS; COMPUTATION THEORY; COMPUTATIONAL COMPLEXITY; CONVOLUTION; COSINE TRANSFORMS; TABLE LOOKUP;

SYSTEMS ANALYSIS;

EID: 33749843835     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2006.880191     Document Type: Article

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