Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 6, 2005, Pages 1125-1137

  Chiper, Doru Florin ^a   Swamy, M N S ^a   Ahmad, M Omair ^a   Stouraitis, Thanos ^b  

^a Gina Cody School of Engineering and Computer Science   (Canada)

^b UNIVERSITY OF PATRAS   (Greece)

Author keywords

Forward and inverse cosine and sine transforms; Memory based implementation techniques; Systolic arrays; Very large scale integration (VLSI) algorithms

Indexed keywords

ALGORITHMS; CONVOLUTION; COSINE TRANSFORMS; MATRIX ALGEBRA; ROM; SYSTOLIC ARRAYS;

DISCRETE COSINE TRANSFORM; DISCRETE SINE TRANSFORM; INVERSE COSINE TRANSFORM; INVERSE SINE TRANSFORM; MEMORY BASED IMPLEMENTATION TECHNIQUES; VERY LARGE SCALE INTEGRATION (VLSI) ALGORITHMS;

VLSI CIRCUITS;

EID: 22144453965     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.849109     Document Type: Article

References (30)

1. N. Ahmed, T. Natarajan, and K. R. Rao, "Discrete cosine transform," IEEE Trans. Comput., vol. C-23, no. 1, pp. 90-94, Jan. 1974.
2. H. B. Kekre and J. K. Solanki, "Comparative performance of various trigonometric unitary transforms for transform image coding," Int. J. Electron., vol. 44, no. 3, pp. 305-315, 1978.
3. A. K. Jain, "A fast Karhunen-Loeve transform for a class of random processes," IEEE Trans. Comm., vol. COM-24, no. 10, pp. 1023-1029, Oct. 1976.
4. A. K. Jain, Fundamentals of Digital Image Processing. Englewood Cliffs, NJ: Prentice-Hall, 1989.
5. K. Rose, A. Heiman, and I. Dinstein, "DCT/DST alternate-transform of image coding," IEEE Trans. Comm., vol. 38, no. 1, pp. 94-101, Jan. 1990.
6. U. T. Koc and K. J. R. Liu, "Discrete cosine/sine transform based motion estimation," in Proc. IEEE Int. Conf. Image Processing, vol. 3, 1994, pp. 771-775.
7. D. Sundararajan, M. O. Ahmad, and M. N. S. Swamy, "Vector computation of the discrete Fourier transform," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 4, pp. 449-461, Apr. 1998.
8. V. Britanak, "DCT/DST universal computational structure and its impact on VLSI design," in Proc. IEEE DSP Workshop, Hunt, TX, Oct. 15-18, 2000.
9. L-P. Chau and W-C. Siu, "Direct formulation for the realization of discrete cosine transform using recursive filter structure," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 1, pp. 50-52, Jan. 1995.
10. J. F. Yang and C-P. Fang, "Compact recursive structures for discrete cosine transform," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 4, pp. 314-321, Apr. 2000.
11. W. H. Fang and M. L. Wu, "An efficient unified systolic architecture for the computation of discrete trigonometric transforms," in Proc. IEEE Symp. Circuits and Systems, vol. 3, 1997, pp. 2092-2095.
12. W. H. Fang and M-L. Wu, "Unified fully-pipelined implementations of one- and two-dimensional real discrete trigonometric transforms," IEICE Trans. Fund. Electron. Commun. Comput. Sci., vol. E82-A, no. 10, pp. 2219-2230, Oct. 1999.
13. C. M. Rader, "Discrete Fourier transform when the number of data samples is prime," Proc. IEEE, vol. 56, no. 6, pp. 1107-1108, Jun. 1968.
14. J. Guo, C. M. Liu, and C. W. Jen, "The efficient memory-based VLSI array design for DFT and DCT," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 10, pp. 436-442, Oct. 1992.
15. Y. H. Chan and W. C. Siu, "On the realization of discrete cosine transform using the distributed arithmetic," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 39, no. 9, pp. 705-712, Sep. 1992.
16. D. F. Chiper, M. N. S. Swamy, M. O. Ahmad, and T. Stouraitis, "A systolic array architecture for the discrete sine transform," IEEE Trans. Signal Process., vol. 50, no. 9, pp. 2347-2353, Sep. 2002.
17. S. A. White, "Applications of the distributed arithmetic to digital signal processing: A tutorial review," IEEE ASSP Mag., vol. 6, no. 3, pp. 5-19, Jul. 1989.
18. H. T. Kung, "Why systolic architectures," IEEE Comp., vol. 15, pp. 37-46, Jan. 1982.
19. S. Yu and E. E. Swartzlander, "DCT implementation with distributed arithmetic," IEEE Trans. Comp., vol. 50, no. 9, pp. 985-991, Sep. 2001.
20. M. T. Sun et al., "VLSI implementation of a 16 × 16 discrete cosine transform," IEEE Trans. Circuits Syst., vol. 36, no. 4, pp. 610-617, Apr. 1989.
21. S. Uramoto et al., "A 100 MHz 2-D discrete cosine transform core processor," IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 482-498, Apr. 1992.
22. D. F. Chiper, "A systolic array algorithm for an efficient unified memory-based implementation of the inverse discrete cosine transform," in Proc. IEEE Conf. Image Processing, Kobe, Oct. 1999, pp. 764-768.
23. S. B. Pan and R-H. Park, "Unified systolic array for computation of DCT/ DST/DHT," IEEE Trans. Circuits Syst. Video Technol., vol. 7, no. 2, pp. 413-419, Apr. 1997.
24. L. W. Chang and W. C. Wu, "A unified systolic array for discrete cosine and sine transforms," IEEE Trans. Signal Process., vol. 39, no. 1, pp. 192-194, Jan. 1991.
25. J-I. Guo and C-C. Li, "A generalized architecture for the one-dimensional discrete cosine and sine transforms," IEEE Trans. Circuits Syst. Video Technol., vol. 11, no. 7, pp. 874-881, Jul. 2001.
26. J. Guo, C. Chen, and C-W. Jen, "Unified array architecture for DCT/ DST and their inverses," Electron. Lett., vol. 31, no. 21, pp. 1811 - 1812, 1995.
27. J. G. McWhirter, "Algorithmic engineering in adaptive signal processing," Proc. Inst. Elect. Eng. F, vol. 139, no. 3, pp. 226-232, Jun. 1992.
28. S. Y. Kung, VLSI Array Processors. Englewood Cliffs, NJ: Prentice-Hall, 1988.
29. C. W. Jen and H. Y. Hsu, "The design of systolic arrays with tag input," in Proc. IEEE Int. Symp. Circuits and Systems ISCAS'88, Finland, 1988, pp. 2263-2266.
30. N. R. Murthy and M. N. S. Swamy, "On the real-time computation of DFT and DCT through systolic arrays," IEEE Trans. Signal Process, vol. 42, no. 4, pp. 988-991, Apr. 1994.