3-dimensional systolic architecture for parallel VLSI implementation of the discrete cosine transform

IEE Proceedings: Circuits, Devices and Systems

Volumn 143, Issue 5, 1996, Pages 255-258

  Nayak, S S ^a   Meher, P K ^a  

^a SKCG College   (India)

Author keywords

Discrete cosine transform; Signal processing; Systolic algorithms; VLSI

Indexed keywords

DIGITAL SIGNAL PROCESSING; MATHEMATICAL TRANSFORMATIONS; PIPELINE PROCESSING SYSTEMS; THREE DIMENSIONAL COMPUTER GRAPHICS; VLSI CIRCUITS;

DISCRETE COSINE TRANSFORMS (DCT); ORTHOGONAL ALIGNMENT;

SYSTOLIC ARRAYS;

EID: 0030260170     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:19960347     Document Type: Article

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