New systolic array algorithm for memory-based VLSI array implementation of DCT

IEEE Symposium on Computers and Communications - Proceedings

Volumn , Issue , 1997, Pages 297-301

  Chiper, Doru Florin ^a  

^a GHEORGHE ASACHI TECHNICAL UNIVERSITY OF IASI   (Romania)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; MATHEMATICAL TRANSFORMATIONS; PARALLEL PROCESSING SYSTEMS; ROM; VLSI CIRCUITS;

DISCRETE COSINE TRANSFORM (DCT);

SYSTOLIC ARRAYS;

EID: 0030713256     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)