A systolic array architecture for the discrete sine transform

IEEE Transactions on Signal Processing

Volumn 50, Issue 9, 2002, Pages 2347-2354

  Chiper, Doru Florin ^b   Swamy, M N S ^a,c   Ahmad, M Ohmair ^a,c   Stouraitis, Thanos ^a,d  

^a IEEE   (Canada)

^b GHEORGHE ASACHI TECHNICAL UNIVERSITY OF IASI   (Romania)

^c Gina Cody School of Engineering and Computer Science   (Canada)

^d UNIVERSITY OF PATRAS   (Greece)

Author keywords

Discrete sine transform; Systolic arrays; VLSI algorithms

Indexed keywords

ALGORITHMS; BLOCK CODES; MATHEMATICAL MODELS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

DISCRETE SINE TRANSFORMS (DCT);

IMAGE PROCESSING;

EID: 0036725647     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2002.801940     Document Type: Article

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