A 0.6 to 9.6Gb/s binary backplane transceiver core in 0.13μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Krishna, Kannan ^a   Yokoyama Martin, David A ^a   Wolfer, Skye ^a   Jones, Chris ^b   Loikkanen, Mat ^a   Parker, James ^a   Segelken, Ross ^a   Sonntag, Jeff L ^a   Stonick, John ^a   Titus, Steve ^c   Weinlader, Daniel ^a  

^a SYNOPSYS INC   (United States)

^b Stexar   (United States)

^c UNIVERSITY OF NORTH CAROLINA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144444841     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. Qureshi, "Adaptive Equalization," IEEE Communications Magazine, vol. 20, no. 2, pp.9-16, Mar., 1982.
2. S. Kasturia et al., "Adaptive Nonlinear Cancellation for High-Speed Fiber-Optic Systems," IEEE J. Lightwave Tech., vol 10, no 7, July, 1992.
3. Accelerant Networks, "AN6420 Quad 6.25Gb/s Low Power 2:1 MUX/DEMUX Continuously Adaptive Backplane Transceiver," May, 2003.
4. H. Lee et al., "A Fully Integrated 0.13μm CMOS 10Gb Ethernet Transceiver with XAUI Interface," ISSCC Dig. Tech. Papers, pp. 170-171, Feb., 2004.
5. K. Chang et al., "A 0.4-4Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs," J. Solid-State Circuits, vol. 38,pp. 747-754, May, 2003.