A 1-tap 40-Gbps look-ahead decision feedback equalizer in 0.18μm SiGe BiCMOS technology

Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

Volumn , Issue , 2005, Pages 37-40

  Garg, Adesh ^a   Carusone, Anthony Chan ^a   Voinigescu, Sorin P ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; SEMICONDUCTING SILICON COMPOUNDS; VOLTAGE CONTROL;

BICMOS TECHNOLOGY; HIGH SPEED CLOCK DISTRIBUTION;

DECISION FEEDBACK EQUALIZERS;

EID: 30944450843     PISSN: 15508781     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. J. Sewter and A. Chan Carusone, "A 40 Gb/s Transversal Filter in 0.18μm CMOS Using Distributed Amplifiers," in IEEE CICC, Sept 2005.
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5. H. Bülow, et al., "PMD mitigation at 10Gb/s using linear and nonlinear integrated electronic equaliser circuits," Electronics Letters, vol. 36, no. 2, pp. 163-164, 2000.
6. M. Nakamura, et al., "Electrical PMD equalizer ICs for a 40-Gbit/s transmission," in Proc. Optical Fiber Communication Conference, Feb. 2004, p. 3.
7. S. Kasturia and J. H. Winters, "Techniques for high-speed implementation of nonlinear cancellation," IEEE Journal on Selected Areas in Communications, vol. 9, no. 5, pp. 711-717, June 1991.
8. S. Voinigescu, et al., "Algorithmic Design Methodologies and Design Porting of Wireline Transceiver IC Building Blocks Between Technology Nodes," in Proc. IEEE CICC (Invited). 2005.