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Volumn 2006, Issue , 2006, Pages 147-152

An efficient wrapper scan chain configuration method for Network-on-Chip testing

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; TELECOMMUNICATION NETWORKS;

EID: 33749344258     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2006.21     Document Type: Conference Paper
Times cited : (19)

References (13)
  • 1
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. Inpmc. of Design Automation Conf., pages 684-689, 2001.
    • (2001) Inpmc. of Design Automation Conf. , pp. 684-689
    • Dally, W.J.1    Towles, B.2
  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan
    • L. Benini and G. D. Micheli. Networks on chips: a new SoC paradigm. IEEE Computer, 35:70-78, Jan 2002.
    • (2002) IEEE Computer , vol.35 , pp. 70-78
    • Benini, L.1    Micheli, G.D.2
  • 5
    • 0346119949 scopus 로고    scopus 로고
    • Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip
    • Dec
    • V. Iyengar, K. Chakrabarty, and E.J. Marinissen. Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip. IEEE tranc. on Computers, pages 1619 -1632, Dec 2003.
    • (2003) IEEE Tranc. on Computers , pp. 1619-1632
    • Iyengar, V.1    Chakrabarty, K.2    Marinissen, E.J.3
  • 6
    • 0034483643 scopus 로고    scopus 로고
    • An ILP formulation to optimize test access mechanism in system-on-chip testing
    • M. Nourani and C. Papachristou. An ILP formulation to optimize test access mechanism in system-on-chip testing. In proc. of International Test Conference, pages 902-1000, 2000.
    • (2000) Proc. of International Test Conference , pp. 902-1000
    • Nourani, M.1    Papachristou, C.2
  • 9
    • 84886567968 scopus 로고    scopus 로고
    • Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking
    • C. Liu, V. Iyengar, J. Shi, and E. Cota. Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking. In proc. of IEEE VLSI Test Symp., pages 349-354, 2005.
    • (2005) Proc. of IEEE VLSI Test Symp. , pp. 349-354
    • Liu, C.1    Iyengar, V.2    Shi, J.3    Cota, E.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.