Nanowire addressing in the face of uncertainty

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

Volumn 2006, Issue , 2006, Pages 225-230

  Rachlin, Eric ^a   Savage, John E ^a  

^a Brown Univerity   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODERS; MESO-SCALE WIRES (MW); NANOWIRES (NW); RESISTIVE SWITCHES;

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DECODING; EMBEDDED SYSTEMS; FAULT TOLERANT COMPUTER SYSTEMS; INTERFACES (COMPUTER);

UNCERTAIN SYSTEMS;

EID: 33749341858     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2006.66     Document Type: Conference Paper

References (14)

1. S. Y. Chou, P. R. Krauss, and P. J. Renstrom. Imprint lithography with 25-nanometer resolution. Science, 272:85-87, 1996.
2. W. Wu, G. Y. Jung, D. L. Olynick, J. Straznicky, Z. Li, X. Li, D. A. A. Ohlberg, Y. Chen, William M. Tong, S.-Y. Wang, J. A. Liddle, W. M. Tong, and R. Stanley Williams. One-kilobit cross-bar molecular memory circuits at 30nm half-pitch fabricated by nanoimprint lithography. Applied Physics A, 80:1173-1178, 2005.
3. Nicholas A. Melosh, Akram Boukai, Frederic Diana. Brian Gerardot, Antonio Badolato, Pierre M. Petroff, and James R. Heath. Ultrahigh-density nanowire lattices and circuits. Science, 300:112-115. Apr. 4, 2003.
4. E. Johnston-Halperin, R. Beckman, Y. Luo, N. Melosh, J. Green, and J.R. Heath. Fabrication of conducting silicon nanowire arrays. J. Applied Physics Letters, 96(10):5921-5923, 2004.
5. R. S. Williams and P. J. Kuekes. Demultiplexer for a molecular wire crossbar network, US Patent Number 6,256,767, July 3, 2001.
6. Eric Rachlin, John E Savage, and Benjamin Gojman. Analysis of a mask-based nanowire decoder. In Procs 2005 Int. Symp. on VLSI. Tampa, FL, May 11-12, 2005.
7. Robert Beckman, Ezekiel Johnston-Halperin, Yi Luo, Jonathan E. Green, and James R. Heath. Bridging dimensions: Demultiplexing ultrahigh-density nanowire circuits. Science. 310:465-468, 2005.
8. Y. Huang, X. Duan, Q. Wei, and C. M. Lieber. Directed assembly of one-dimensional nanostructures into functional networks. Science, 291:630-633, 2001.
9. André Dehon. Deterministic addressing of nanoscale devices assembled at sublithographic pitches. IEEE Transactions on Nanotechnology. 4(6):681-687, 2005.
10. Benjamin Gojman, Eric Rachlin, and John E. Savage. Evaluation of design strategies for stochastically assembled nanoarray memories. J. Emerg. Technol. Comput. Syst., 1(2):73-108, 2005.
11. André DeHon, Patrick Lincoln. and John E. Savage. Stochastic assembly of sublithographic nanoscale interfaces. IEEE Transactions on Nanotechnology. 2(3): 165-174, 2003.
12. Philip J Kuekes, Warren Robinett, Gabriel Seroussi, and R Stanley Williams. Defect-tolerant interconnect to nanoelectronic circuits. Nanotechnology. 16:869-882, 2005.
13. Philip J Kuekes, Warren Robinett, and R Stanley Williams. Improved voltage margins using linear error correcting-codes in resistor-logic demultiplexers for nanoelectronics. Nanotechnology, 16:1419-1432, 2005.
14. H. Chernoff. A measure of asymptotic efficiency for tests of a hypothesis based on a sum of observations. Ann. Math. Stat., 23:493-507, 1960.