Fast buffer planning and congestion optimization in interconnect-driven floorplanning

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2003-January, Issue , 2003, Pages 411-416

  Wong, K W C ^a   Young, E F Y ^a  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; COMPUTER AIDED DESIGN;

BUFFER BLOCK PLANNING; BUFFER INSERTION; BUFFER PLANNING; CONGESTION ESTIMATION; ESTIMATION PROCESS; FLOOR-PLANNING; PHYSICAL DESIGN; PROBABILISTIC ANALYSIS;

DYNAMIC PROGRAMMING;

EID: 11144238859     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195050     Document Type: Conference Paper

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