-
2
-
-
0030243819
-
Energy dissipation in general purpose microprocessors
-
September
-
R. Gonzalez and M. Horowitz, Energy Dissipation in General Purpose Microprocessors, IEEE Journal of Solid-State Circuits, 9(21):1277-1284 (September 1996).
-
(1996)
IEEE Journal of Solid-state Circuits
, vol.9
, Issue.21
, pp. 1277-1284
-
-
Gonzalez, R.1
Horowitz, M.2
-
4
-
-
0036110799
-
Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading
-
R. P. Preston et al., Design of an 8-Wide Superscalar RISC Microprocessor with Simultaneous Multithreading, International Solid-State Circuits Conference (2002).
-
(2002)
International Solid-state Circuits Conference
-
-
Preston, R.P.1
-
7
-
-
0032629113
-
Hardware-driven profiling scheme for identifying program hot spots to support runtime optimization
-
M. C. Merten, A. R. Trick, C. N. George, J. C. Gyllenhaal, and W. W. Hwu, Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization, International Symposium on Computer Architecture (1999).
-
(1999)
International Symposium on Computer Architecture
-
-
Merten, M.C.1
Trick, A.R.2
George, C.N.3
Gyllenhaal, J.C.4
Hwu, W.W.5
-
8
-
-
3543104761
-
Dynamically reconfiguring processor resources to reduce power consumption in high-performance processors
-
R. Maro, Y. Bai, and R. I. Bahar, Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors, Workshop on Power Aware Computing Systems (2000).
-
(2000)
Workshop on Power Aware Computing Systems
-
-
Maro, R.1
Bai, Y.2
Bahar, R.I.3
-
10
-
-
2342649456
-
Architectural and compiler strategies for dynamic power management in the COPPER project
-
A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau, Architectural and Compiler Strategies for Dynamic Power Management in the COPPER Project, International Workshop on Innovative Architecture (2001).
-
(2001)
International Workshop on Innovative Architecture
-
-
Azevedo, A.1
Issenin, I.2
Cornea, R.3
Gupta, R.4
Dutt, N.5
Veidenbaum, A.6
Nicolau, A.7
-
11
-
-
84893766434
-
Profile-based dynamic voltage scheduling using program checkpoints in the COPPER framework
-
A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum, and A. Nicolau, Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints in the COPPER Framework, Design and Test in Europe (2002).
-
(2002)
Design and Test in Europe
-
-
Azevedo, A.1
Issenin, I.2
Cornea, R.3
Gupta, R.4
Dutt, N.5
Veidenbaum, A.6
Nicolau, A.7
-
16
-
-
1142280977
-
Reducing register ports using delayed write-back queues and operand pre-fetch
-
N. S. Kim and T. Mudge, Reducing Register Ports Using Delayed Write-Back Queues and Operand Pre-Fetch, International Conference on Supercomputing (2003).
-
(2003)
International Conference on Supercomputing
-
-
Kim, N.S.1
Mudge, T.2
-
17
-
-
52949142619
-
Energy aware register file implementation through instruction predecode
-
J. L. Ayala, M. López-Vallejo, A. Veidenbaum, and C. A. López, Energy Aware Register File Implementation Through Instruction Predecode, International Conference on Application-Specific Systems, Architectures and Processors (2003).
-
(2003)
International Conference on Application-specific Systems, Architectures and Processors
-
-
Ayala, J.L.1
López-Vallejo, M.2
Veidenbaum, A.3
López, C.A.4
-
18
-
-
3543058029
-
Scalar program performance on multiple-instruction issue processors with a limited number of registers
-
S. A. Mahlke, W. Y. Chen, P. P. Chang, and W. Hwu, Scalar Program Performance on Multiple-Instruction Issue Processors with a Limited Number of Registers, Hawaii International Conference on System Sciences, pp. 34-44 (1992).
-
(1992)
Hawaii International Conference on System Sciences
, pp. 34-44
-
-
Mahlke, S.A.1
Chen, W.Y.2
Chang, P.P.3
Hwu, W.4
-
19
-
-
0042851931
-
-
Technical Report CSE-TR-434-00, Electrical Engineering and Computer Science Department, The University of Michigan, USA
-
M. Postiff, D. Greene, and T. Mudge, The Need for Large Register File in Integer Codes, Technical Report CSE-TR-434-00, Electrical Engineering and Computer Science Department, The University of Michigan, USA (2000).
-
(2000)
The Need for Large Register File in Integer Codes
-
-
Postiff, M.1
Greene, D.2
Mudge, T.3
-
21
-
-
0036294454
-
Drowsy caches: Simple techniques for reducing leakage power
-
K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and M. T, Drowsy Caches: Simple Techniques for Reducing Leakage Power, International Symposium on Computer Architecture (2002).
-
(2002)
International Symposium on Computer Architecture
-
-
Flautner, K.1
Kim, N.S.2
Martin, S.3
Blaauw, D.4
-
22
-
-
3543049912
-
-
Technical Manual
-
ARM, ARM7TDMI, Technical Manual (2001).
-
(2001)
ARM7TDMI
-
-
-
23
-
-
84893776167
-
An efficient compiler technique for code size reduction using reduced bit-width ISAs
-
A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau, An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs, Design and Test in Europe (2002).
-
(2002)
Design and Test in Europe
-
-
Halambi, A.1
Shrivastava, A.2
Biswas, P.3
Dutt, N.4
Nicolau, A.5
-
24
-
-
3543134062
-
Profile guided selection of ARM and thumb instructions
-
A. Krishnaswamy and R. Gupta, Profile Guided Selection of ARM and Thumb Instructions, ACM SIGPLAN (2002).
-
(2002)
ACM SIGPLAN
-
-
Krishnaswamy, A.1
Gupta, R.2
-
25
-
-
0036469652
-
Simplescalar: An infrastructure for computer system modeling
-
February
-
T. Austin, E. Larson, and Dan Ernst, Simplescalar: An Infrastructure for Computer System Modeling, Computer, 35(2): 59-67 (February 2002).
-
(2002)
Computer
, vol.35
, Issue.2
, pp. 59-67
-
-
Austin, T.1
Larson, E.2
Ernst, D.3
-
27
-
-
0003650381
-
-
Technical Report 93/5, Computer Science Department, University of Wisconsin-Madison, USA
-
S. J. E. Wilton and N. P. Jouppi, An Enhanced Access and Cycle Time Model for On-Chip Caches, Technical Report 93/5, Computer Science Department, University of Wisconsin-Madison, USA (1994).
-
(1994)
An Enhanced Access and Cycle Time Model for on-chip Caches
-
-
Wilton, S.J.E.1
Jouppi, N.P.2
-
28
-
-
84962779213
-
MiBench: A free, commercially representative embedded benchmark suite
-
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown, MiBench: A Free, Commercially Representative Embedded Benchmark Suite, Annual Workshop on Workload Characterization (2001).
-
(2001)
Annual Workshop on Workload Characterization
-
-
Guthaus, M.R.1
Ringenberg, J.S.2
Ernst, D.3
Austin, T.M.4
Mudge, T.5
Brown, R.B.6
|