PBExplore: A framework for compiler-in-the-loop exploration of partial bypassing in embedded processors

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1264-1269

  Shrivastava, Aviral ^a   Dutt, Nikil ^a   Nicolau, Alex ^a   Earlie, Eugene ^b  

^a Ringgold Standard Institution Informatics   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BYPASS DESIGN; COMPILER-IN-THE-LOOP; EMBEDDED PROCESSORS; PIPELINED PROCESSORS;

BENCHMARKING; COMPUTER ARCHITECTURE; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; PROGRAM PROCESSORS; SYSTEMS ANALYSIS;

EMBEDDED SYSTEMS;

EID: 33646911078     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.236     Document Type: Conference Paper

References (13)

1. A. Abnous and N. Bagerzadeh. Pipelining and bypassing in a vliw processor. In IEEE trans. on PDS, 1995.
2. P. Ahuja, D. W. Clark, and A. Rogers. The performance impact of incomplete bypassing in processor pipelines. In Proc. of MICRO-28, 1995.
3. E. Bloch. The engineering design of the stretch computer. In Proc. of EJCC, pages 48-59, 1959.
4. M. Buss, R. Azavedo, P. Centoducatte, and G. Araujo. Tailoring pipeline bypassing and functional unit mapping for application in clustered vliw architectures. In Proc. of CASES, 2001.
5. R. Cohn, T. Gross, M. Lam, and P. Tseng. Architecture and compiler tradeoffs for a long instruction word microprocessor. In Proc. of ASPLOS, 1989.
6. K. Fan, N. Clark, M. Chu, K. V. Manjunath R. Ravindran, M. Smelyanskiy, and S. Mahlke. Systematic register bypass customization for application-specific processors. In Proc. of ASSAP, 2003.
7. J. Gray, A. Naylor, A. Abnous, and N. Bagherzadheh. Viper: A vliw integer microprocessor. In IEEE Journal of Solid State Circuits, pages 1377-1383, 1993.
8. M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. Mibench: A free, commercially representative embedded benchmark suite. In IEEE Workshop in workload characterization, 2001.
9. P. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, 1990.
10. http://www.intel.com/design/intelxscale/273436.htm. Intel XScale Microarchitecture Programmers Reference, 2001.
11. http://www.synopsys.com/products/logic/design_compiler.html. Synopsys Design Compiler, 2001.
12. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, 1998.
13. A. Shrivastava, E. Earlie, N. Dutt, and A. Nicolau. Operation tables for scheduling in the presence of incomplete bypassing. In Proc. of CODES+ISSS 2004, 2004.