Charge retention enhancement in stack nanocrystalline-Si based metal-insulator-semiconductor memory structure

Applied Physics Letters

Volumn 89, Issue 11, 2006, Pages

  Wu, L C ^a,b   Chen, K J ^b   Wang, J M ^b   Huang, X F ^b   Song, Z T ^a   Liu, W L ^a  

^a SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY   (China)

^b NANJING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; ELECTRIC CURRENTS; ELECTRIC INSULATORS; ELECTRONS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; RESONANT TUNNELING; SEMICONDUCTOR STORAGE; SILICON;

ASYMMETRIC CURRENTS; CAPACITANCE HYSTERESIS; CHARGE STORAGE ABILITY;

NANOSTRUCTURED MATERIALS;

EID: 33748685259     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.2352796     Document Type: Article

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