Energy estimation based on hierarchical bus models for power-aware smart cards

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn , Issue , 2004, Pages 300-305

  Neffe, U ^a   Rothbart, K ^a   Steger, Ch ^a   Weiss, R ^a   Rieger, E ^b   Muhlberger A ^b  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFERENTIAL POWER ANALYSIS (DPA); ENERGY ESTIMATION; REGISTER-TRANSFER-LEVEL (RTL); SIMPLE POWER ANALYSIS (SPA);

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTER HARDWARE; COMPUTER SIMULATION; DATA REDUCTION; ENERGY UTILIZATION; ESTIMATION; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PROBABILITY; SYSTEMS ANALYSIS;

SMART CARDS;

EID: 3042520667     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269254     Document Type: Conference Paper

References (10)

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