Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA)

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 718-723

  Agarwal, Vineet ^a   Wang, Janet ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GENETIC ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; OPTIMAL CONTROL SYSTEMS; OPTIMIZATION; PARETO PRINCIPLE; PROBLEM SOLVING;

FUNCTIONALLY RELIABLE CIRCUITS; GATE SIZING; NON-DOMINATED SORTING GENETIC ALGORITHM (NSGA); SHRINKING TECHNOLOGY;

DIGITAL CIRCUITS;

EID: 33748628227     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118467     Document Type: Conference Paper

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