Optimal transistor sizing for CMOS VLSI circuits using modular artificial neural networks

Proceedings of the Annual Southeastern Symposium on System Theory

Volumn , Issue , 1997, Pages 310-313

  Ilumoka, A A ^a  

^a UNIVERSITY OF HARTFORD   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT MANUFACTURE; MICROELECTRONIC PROCESSING; NEURAL NETWORKS; OPTIMIZATION; TRANSISTORS; VLSI CIRCUITS;

MAXIMIZATION; MINATURIZATION; OPTIMAL TRANSISTOR SIZING; QUADRATIC HYPERSURFACE FITTING; SPICE SIMULATION;

COMPUTER AIDED MANUFACTURING;

EID: 0030706504     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)