Improving the process-variation tolerance of digital circuits using gate sizing and statistical techniques

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 294-299

  Neiroukh, Osama ^a   Song, Xiaoyu ^b  

^a INTEL CORPORATION   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; STATISTICAL METHODS; TIMING CIRCUITS;

CIRCUIT OPTIMIZATION; PROCESS VARIATION TOLERANCE; RANDOM VARIABLES; STATISTICAL CRITICAL PATHS; STATISTICAL TIMING ANALYSIS;

DIGITAL CIRCUITS;

EID: 33646901050     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.180     Document Type: Conference Paper

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