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Volumn 2006, Issue , 2006, Pages 84-89

Process-induced skew reduction in nominal zero-skew clock trees

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; MONTE CARLO METHODS; SAMPLING; SENSITIVITY ANALYSIS;

EID: 33748605033     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118319     Document Type: Conference Paper
Times cited : (12)

References (14)
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    • Abbaspour, S.1    Fantemi, H.2    Pedram, M.3
  • 2
    • 0346778703 scopus 로고    scopus 로고
    • Statistical clock skew analysis considering intra-die process variations
    • A. Agarwal, D. Blaauw, and V. Zolotov. Statistical clock skew analysis considering intra-die process variations. In ICCAD, pages 914-920, 2003.
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    • Agarwal, A.1    Blaauw, D.2    Zolotov, V.3
  • 3
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    • Variational delay metrics for interconnect timing analysis
    • K. Agarwal, D. Sylvester, and D. Blaauw. Variational delay metrics for interconnect timing analysis. In DAC, 2004.
    • (2004) DAC
    • Agarwal, K.1    Sylvester, D.2    Blaauw, D.3
  • 4
    • 33747993282 scopus 로고
    • Zero-skew clock routing trees with minimum wirelength
    • K. Boese and A. Kahng. Zero-skew clock routing trees with minimum wirelength. In ASIC Conf., pages 1.1.1-1.1.5, 1992.
    • (1992) ASIC Conf.
    • Boese, K.1    Kahng, A.2
  • 5
    • 84949480508 scopus 로고    scopus 로고
    • Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI
    • September
    • Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang. Design sensitivities to variability: Extrapolations and assessments in nanometer VLSI. In ASIC/SOC, pages 411-415, September 2002.
    • (2002) ASIC/SOC , pp. 411-415
    • Cao, Y.1    Gupta, P.2    Kahng, A.B.3    Sylvester, D.4    Yang, J.5
  • 6
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    • Zero skew clock net routing
    • T.-H. Chao, Y.-C. Hsu, and J. Ho. Zero skew clock net routing. In DAC, pages 518-523, 1992.
    • (1992) DAC , pp. 518-523
    • Chao, T.-H.1    Hsu, Y.-C.2    Ho, J.3
  • 7
    • 0029204493 scopus 로고
    • Minimum-cost bounded-skew clock routing
    • J. Cong and C.-K. Koh. Minimum-cost bounded-skew clock routing. In ISCAS, pages 215-218, 1995.
    • (1995) ISCAS , pp. 215-218
    • Cong, J.1    Koh, C.-K.2
  • 9
    • 0029225165 scopus 로고
    • On the bounded-skew clock and steiner routing problems
    • June
    • D. J.-H. Huang, A. B. Kahng, and C.-W. A. Tsao. On the bounded-skew clock and steiner routing problems. In DAC. 508-513, June 1995.
    • (1995) DAC , pp. 508-513
    • Huang, D.J.-H.1    Kahng, A.B.2    Tsao, C.-W.A.3
  • 10
    • 16244417469 scopus 로고    scopus 로고
    • A novel clock distribution and dynamic de-skewing methodology
    • A. Kapoor, N. Jayakumar, and S. P. Khatri. A novel clock distribution and dynamic de-skewing methodology. In ICCAD, pages 626-631, 2004.
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    • Kapoor, A.1    Jayakumar, N.2    Khatri, S.P.3
  • 11
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    • Process variation aware clock tree routing
    • B. Lu, J. Hu, G. Ellis, and H. Su. Process variation aware clock tree routing. In ISPD, pages 174-181, 2003.
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    • The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes
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    • B. E. Stine and D. S. B. et al. The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes. IEEE Transactions on Electron Devices, 45(3):665-679, March 1998.
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    • J.-L. Tsai, D.-H. Baik, C. C. Chen, and K. K. Saluja. A yield improvement methodology using pre- and post-silicon statistical clock scheduling. In ICCAD, pages 611-618, 2004.
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    • Tsai, J.-L.1    Baik, D.-H.2    Chen, C.C.3    Saluja, K.K.4
  • 14


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.