Toward ultra-low power III-V quantum large scale integrated circuits for ubiquitous network era

International Journal of High Speed Electronics and Systems

Volumn 16, Issue 2, 2006, Pages 421-436

  Hasegawa, Hideki ^a   Kasai, Seiya ^a   Sato, Taketomo ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

Author keywords

III V compound semiconductors; Nanoelectronics

Indexed keywords

COMBINATORIAL CIRCUITS; LOGIC CIRCUITS; NANOSTRUCTURED MATERIALS; QUANTUM ELECTRONICS; SEMICONDUCTOR MATERIALS; SWITCHING;

BINARY-DECISION DIAGRAMS (BDD); III-V COMPOUND SEMICONDUCTORS; NANOELECTRONICS; SCHOTTKY WRAP GATES (WPGS);

INTEGRATED CIRCUITS;

EID: 33748442864     PISSN: 01291564     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0129156406003758     Document Type: Conference Paper

References (31)

1. International Technology Roadmap for Semiconductors, see web site, http://public.itrs.net/
2. see for example, Special Section on New System Paradigms for Integrated Electronics, IEICE Trans. Electron. E87-C(11) (2004).
3. M. Usami and M. Ohki, The μ-Chip: An ultra-small 2.45 GHz RFID chip for ubiquitous recognition application, IEICE Trans. Electron. E86-C(4), 521-528 (2003).
4. Intel web site, http://www.intel.co.jp/research/exploratory/ wireless_sensors.htm
5. International Technology Roadmap for Semiconductors, Emerging Research Devices, http://www.itrs.net/Common/2004Update/2004Update.htm
6. R. Chau, Advanced CMOS transistors in the nanotechnology era for high-performance, low-power applications, presented at the 7th International Conference on Solid-State and Integrated-Circuit Technology, October 18-21, 2004, Beijing, China.
7. S. Datta, R. Chau, T. Ashley, A. R. Barnes, L. Buckle, A. B. Dean, M. T. Emeny, M. Fearn, D. G. Hayes, K. P. Hilton, R. Jefferies, T. Martin, K. J. Nash, T. J. Phillips, W. H. A. Tang and P. J. Wilding, Novel InSb-based quantum well transistors for ultra-high speed, low power logic applications, presented at the 7th International Conference on Solid-State and Integrated-Circuit Technology, October 18-21, 2004, Beijing, China.
8. see web site, http://www.rciqe.hokudai.ac.jp/mbe/IQC/IQC_e.html
9. H. Hasegawa and S. Kasai, Hexagonal binary decision diagram quantum logic circuits using Schottky in-plane and wrap-gate control of GaAs and InGaAs nanowires, Physica E, 11, 149-154 (2001).
10. S. Kasai and H. Hasegawa, A single electron binary-decision-diagram quantum logic circuit based on Schottky wrap gate control of a GaAs nanowire hexagon, IEEE Electron Device Lett. 23, 446-448 (2002).
11. P. Gelsigner, Microprocessors for the new millennium: Challenges, opportunities, and new frontiers, 2007 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 22-25 (2001), see also web site: http://www.intel.com/research/silicon/micron.htm
12. M. Saitoh, T. Murakami and T. Hiramoto, Large coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFETs formed by slight oxidation process, IEEE Transactions on Nanotechnology 2(4), 241-245 (2003).
13. J. Koga, R. Ohba, K. Uchida and A. Toriumi, Silicon single-electron memory and logic devices for room temperature operation, 2001 International Electron Devices Meeting Technical Digest, 7.1.1-7.1.4 (2001).
14. S. B. Akers, Binary decision diagrams, IEEE Trans. Compt. C-27, 509-516 (1978).
15. N. Asahi, M. Akazawa, and Y. Amemiya, Binary-decision-diagram device, IEEE Trans. Electron Devices 44, 1109-1116 (1997).
16. S. Kasai, K. Jinushi, H. Tomozawa and H. Hasegawa, Fabrication and characterization of GaAs single electron devices having single and multiple dots based on Schottky in-plane-gate and wrap-gate control of two-dimensional electron gas, Jpn. J. Appl. Phys. 36, 1678-1685 (1997).
17. S. Kasai and H. Hasegawa, GaAs and InGaAs single electron hexagonal nanowire circuits based on binary decision diagram logic architecture, Physica E 13, 925-929 (2002).
18. S. Kasai, M. Yumoto and H. Hasegawa, Fabrication of GaAs-based integrated half and full adders by novel hexagonal BDD quantum circuit approach, Solid State Electron. 47, 199-204 (2003).
19. M. Yumoto, S. Kasai and H. Hasegawa, Novel quantum wire branch-switches for binary decision diagram logic architecture utilizing Schottky wrap-gate control of GaAs/AIGaAs nanowires, Jpn. J. Appl. Phys. 41, 2671-2674 (2002).
20. R. Chau, 30nm and 20nm physical gate length CMOS transistors, presented at 2001 Silicon Nanoelectronics Workshop, June 10-11, 2001, Kyoto, Japan.
21. M. Yumoto, S. Kasai and H. Hasegawa, Speed-power performances of quantum wire switches controlled by nanometer-scale Schottky wrap gates for GaAs based hexagonal BDD quantum LSIs, presented at 31 st International Symposium on Compound Semiconductors, September 12-16, 2004, Seoul, Korea,
22. accepted for publication in IOP Conf. Ser. (2005).
23. E. Kapon, M. C. Tamargo and D. M. Hwang, Molecular beam epitaxy of GaAs/AlGaAs superlattice heterostructures on nonplanar substrates, Appl. Phys. Lett. 50, 347-349 (1987).
24. K. Kumakura, J. Motohisa and T. Fukui, Formation and characterization of coupled quantum dots (CQDs) by selective area metalorganic vapor phase epitaxy, J. Crys. Growth 170, 700-704 (1997).
25. X.-L. Wang, M. Ogura and H. Matsuhata, Flow rate modulation epitaxy of AlGaAs/GaAs quantum wires on nonplanar Substrate, Appl. Phys. Lett. 66, 1506-1508 (1995).
26. H. Hasegawa, H. Fujikura and H. Okada, Molecular beam epitaxy and device applications of III-V semiconductor nanowires, MRS Bulletin 24, 25-30 (1999).
27. T. Sato, I. Tamai, C. Jiang and H. Hasegawa, Selective MBE growth of GaAs/AlGaAs nanowires on patterned GaAs (001) substrates and its application to hexagonal nanowire network formation, IOP Conf. Ser. 170-4, 325-330 (2002).
28. C. Jiang, T. Muranaka and H. Hasegawa, Structural and optical properties of InGaAs ridge quantum wire arrays with sub-micron pitches grown by selective MBE on InP substrates, Jpn. J. Appl. Phys. 41, 2683-2688 (2002).
29. T. Sato, I. Tamai, S. Yoshida and H. Hasegawa, Control of heterointerface cross-sections of GaAs ridge quantum wires by selective molecular beam epitaxy, presented at the 9th International Conference on the Formation of Semiconductor Interfaces, September 15-19, 2003, Madrid, Spain.
30. T. Sato, I. Tamai and H. Hasegawa, Growth kinetics and modeling of selective molecular beam epitaxial growth of GaAs ridge quantum wires on pre-patterned nonplanar substrates, J. Vac. Sci. & Technol. B 22, 2266-2274 (2004).
31. M. T. Bohr, Nanotechnology goals and challenges for electronic applications, IEEE Trans. Nanotech. 1 56-62 (2002), also see, http://www.intel.com/research/silicon/mooreslaw.htm