Placement algorithm in analog-layout designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 1889-1903

  Zhang, Lihong ^b,c   Raut, Rabin ^a,b   Jiang, Yingtao ^a,d   Kleine, Ulrich ^b,e  

^a IEEE

^b Gina Cody School of Engineering and Computer Science   (Canada)

^c DALHOUSIE UNIVERSITY   (Canada)

^d University of Nevada Las Vegas   (United States)

^e OTTO VON GUERICKE UNIVERSITY   (Germany)

Author keywords

Analog integrated circuits (ICs); Genetic algorithm (GA); Layout of integrated circuits; Simulated annealing (SA)

Indexed keywords

COMPUTER AIDED DESIGN; GENETIC ALGORITHMS; PARAMETER ESTIMATION; PROBLEM SOLVING; SIMULATED ANNEALING;

ANALOG INTEGRATED CIRCUITS (ICS); ANALOG MACROCELLS; LAYOUT OF INTEGRATED CIRCUITS; ORTHOGONAL ARRAYS;

INTEGRATED CIRCUITS;

EID: 33748305816     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.860957     Document Type: Article

References (38)

1. M. Wang, X. Yang, and M. Sarrafzadeh, "Dragon2000: Fast standard-cell placement for large circuits," in Proc. IEEE Int. Conf. Computer-Aided Design, San Jose, CA, 2002, pp. 260-263.
2. G. Gielen and R. A. Rutenbar, "Computer-aided design of analog and mixed-signal integrated circuits," Proc. IEEE, vol. 88, no. 12, pp. 1825-1852, Dec. 2000.
3. R. A. Rutenbar and J. M. Cohn, "Layout tools for analog ICs and mixed-signal SoCs: A survey," in Proc. ACM/SIGDA ISPD, San Diego, CA, 2000, pp. 76-83.
4. J. M. Cohn, D. J. Garrod, R. A. Rutenbar, and L. R. Carley, "KOAN/ANAGRAM II: New tools for device-level analog placement and routing," IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 330-342, Mar. 1991.
5. B. Martin, "Automation comes to analog," IEEE Spectr., vol. 38, no. 6, pp. 70-75, Jun. 2001.
6. S. N. Adya and I. L. Markov, "Fixed-outline floorplanning: Enabling hierarchical design," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 11, no. 6, pp. 1120-1135, Jun. 2003.
7. D. F. Wong and C. L. Liu, "A new algorithm for floorplan design," in Proc. 23rd ACM/IEEE Design Automation Conf., Las Vegas, NV, 1986, pp. 101-107.
8. F. Balasa and K. Lampaert, "Symmetry within the sequence-pair representation in the context of placement for analog design," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 7, pp. 721-731, Jul. 2000.
9. F. Balasa, S. Maruvada, and K. Krishnamoorthy, "On the exploration of the solution space in analog placement with symmetry constraints," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 23, no. 2, pp. 177-191, Feb. 2004.
10. K. Lampaert, G. Gielen, and W. Sansen, Analog Layout Generation for Performance and Manufacturability. Boston, MA: Kluwer, 1999.
11. J. Rijmenants, J. B. Litsios, T. R. Schwarz, and M. G. R. Degrauwe, "ILAC: An automated layout tool for analog CMOS circuits," IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 417-425, Apr. 1989.
12. S. W. Mehranfar, "A technology-independent approach to custom analog cell generation," IEEE J. Solid-State Circuits, vol. 26, no. 3, pp. 386-393, Mar. 1991.
13. C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov, and K. Yan, "Quadratic placement revisited," in Proc. 34th ACM/IEEE Design Automation Conf., Anaheim, CA, 1997, pp. 752-757.
14. H. Eisenmann and F. M. Johannes, "Generic global placement and floor-planning," in Proc. 35th ACM/IEEE Design Automation Conf., San Francisco, CA, 1998, pp. 269-274.
15. H. Wang, S. B. K. Vrudhula, and O. A. Palusinski, "Performance driven placement and routing for field programmable analog arrays," in Proc. 8th Int. Conf. Mixed Design Integrated Circuits Systems, Zakopane, Poland, 2001, pp. 207-212.
16. S. Ou and M. Pedram, "Timing-driven placement based on partitioning with dynamic cut-net control," in Proc. 37th ACM/IEEE Design Automation Conf., Los Angeles, CA, 2000, pp. 472-476.
17. J. D. Bruce, H. W. Li, M. J. Dallabetta, and R. J. Baker, "Analog layout using ALAS!," IEEE J. Solid-State Circuits, vol. 31, no. 2, pp. 271-274, Feb. 1996.
18. H. Chan, P. Mazumder, and K. Shahookar, "Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome," Integr. VLSI J., vol. 12, no. 1, pp. 49-77, Nov. 1991.
19. V. Schnecke and O. Vornberger, "Hybrid genetic algorithms for constrained placement problems," IEEE Trans. Evol. Comput., vol. 1, no. 4, pp. 266-277, Nov. 1997.
20. B. H. Gwee and M. H. Lim, "A GA with Heuristic-based decoder for IC floorplanning," Integr. VLSI J., vol. 28, no. 2, pp. 157-172, Jan. 1999.
21. K. Handa and S. Kuga, "Polycell placement for analog LSI Chip designs by genetic algorithms and Tabu search," in Proc. IEEE Conf Evolutionary Computation, Orlando, FL, 1995, vol. 2, pp. 716-721.
22. K. C. Tan, Y. Li, D. J. Murray-Smith, and K. C. Sharman, "System identification and linearisation using genetic algorithms with simulated annealing," in Proc. Ist IEE/IEEE Int. Conf. GA Eng. System: Innovations Applicat., Sheffield, U.K., 1995, pp. 164-169.
23. S. Koatsuku, M. Kang, and W.-M. Dai, "Genetic simulated annealing and application to non-slicing floorplan design," in Proc. 5th ACM/SIGDA Physical Design Workshop, Reston, VA, 1996, pp. 134-141.
24. H. Esbensen and P. Mazumder, "SAGA: A unification of the genetic algorithm with simulated annealing and its application to macro-cell placement," in Proc. 7th Int. Conf. VLSI Design, Calcutta, India, 1994, pp. 211-214.
25. Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, "B*-tree: A new representation for non-slicing floorplans," in Proc. 37th ACM/IEEE Design Automation Conf., Los Angeles, CA, 2000, pp. 458-463.
26. Y. Pang, F. Balasa, K. Lampaert, and C.-K. Cheng, "Block placement with symmetry constraints based on the O-tree non-slicing representation," in Proc. 37th ACM/IEEE Design Automation Conf., Los Angeles, CA, 2000, pp. 464-467.
27. M. Wolf, U. Kleine, and B. Hosticka, "A novel analog module generator environment," in Proc. Eur. Design Test Conf., Paris, France, 1996, pp. 388-392.
28. S. M. Sait and H. Youssef, VLSI Physical Design Automation (Theory and Practice). London, U.K.: McGraw-Hill, 1995.
29. L. Zhang, R. Raut, and Y. Jiang, "A placement algorithm for implementation of analog LSI/VLSI systems," in Proc. IEEE Int. Symp. Circuits Systems, Vancouver, Canada, 2004, pp. V77-V80.
30. P. Mazumder and E. M. Rudnick, Genetic Algorithms (for VLSI Design, Layout & Test Automation). Upper Saddle River, NJ: Prentice-Hall, 1999.
31. S. H. Park, Robust Design and Analysis for Quality Engineering. London, U.K.: Chapman and Hall, 1996.
32. G. Taguchi, Taguchi Methods: Research and Development, vol. 1. Allen Park, MI: Amer. Supplier Inst., 1993.
33. L. Zhang, U. Kleine, R. Raut, and Y. Jiang, "ALADIN: A layout synthesis tool for analog integrated circuits," Int. J. Analog Integr. Circuits Signal Process. to be published.
34. M. Wolf, Konstruktive Layoutgenerierung mit automatischer Neugenerierung unter geänderten Randbedingungen. Aachen, Germany: Shaker, 1999.
35. F. Maloberti, Analog Design for CMOS VLSI Systems. Boston, MA: Kluwer, 2001.
36. T. Pasch, U. Kleine, and R. Klinke, "A common mode feedback structure for differential OpAmps using NMOS depletion transistors," Int. J. Analog Integr. Circuits Signal Process., vol. 27, no. 3, pp. 191-196, May 2001.
37. K. Lampaert, G. Gielen, and W. Sansen, "A performance-driven placement tool for analog integrated circuits," IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 773-780, Jul. 1995.
38. F. Roewer, U. Kleine, K. Salzwedel, F. Mednikov, C. Pfaffinger, and M. Sellen, "A programmable interface circuit for inductive position sensors," in Proc. Southwest Symp. Mixed-Signal Design, Las Vegas, NV, 2003, pp. 175-179.