ADOFs and resistive-ADOFs in SRAM address decoders: Test conditions and march solutions

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 22, Issue 3, 2006, Pages 287-296

  Dilillo, Luigi ^a   Girard, Patrick ^a   Pravossoudovitch, Serge ^a   Virazel, Arnaud ^a   Borri, Simone ^b   Hage Hassan, Magali ^b  

^a UNIVERSITÉ PAUL VALÉRY   (France)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Address decoders; Dynamic faults; Memory testing

Indexed keywords

DECODING; EMBEDDED SYSTEMS; LOGIC GATES; TRANSISTORS;

ADDRESS DECODERS; DYNAMIC FAULTS; MEMORY TESTING;

ELECTRON DEVICE TESTING;

EID: 33747875788     PISSN: 09238174     EISSN: 15730727     Source Type: Journal    
DOI: 10.1007/s10836-006-7761-1     Document Type: Conference Paper

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