A microcode-based memory BIST implementing modified march algorithm

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 391-395

  Youn, Dongkyu ^a   Kim, Taehyung ^a   Park, Sungju ^a  

^a Hanyang University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATA THEORY; DATA STORAGE EQUIPMENT; DECODING; EMBEDDED SYSTEMS; FAILURE ANALYSIS; FIRMWARE; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

ADDRESS DECODER OPEN FAULTS; CELLULAR AUTOMATA; NEIGHBORHOOD PATTERN SENSITIVE FAULTS;

BUILT-IN SELF TEST;

EID: 0035701578     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Automatic failure analysis system for high density DRAM
2. Testing semiconductor memories
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4. Integration of non-classical faults in standard March tests
5. Detection of CMOS address decoder open faults with march and pseudo random memory tests
6. Open defects in CMOS RAM address decoders
7. A built-in self test algorithm for row/column pattern sensitive faults in RAM's
8. A BIST sheme using microprogram ROM for large capacity memories
9. Semiconductor manufacturing process monitoring using BIST for embedded memories
10. On programmable memory built-in self test architectures
11. Analysis of cellular automata used as pseudorandom pattern generators
12. 2-by-n Hybrid cellular automata with regular configuration : Theory and application