A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 8, 2006, Pages 1894-1906

  Loke, Alvin L S ^a,b,c,d   Barnes, Robert K ^a,b   Wee, Tin Tin ^a,b,c,d   Oshima, Michael M ^a,b,e   Moore, Charles E ^a,b   Kennedy, Ronald R ^a,b   Gilsdorf, Michael J ^a,b  

^a IEEE   (United States)

^b BROADCOM CORPORATION   (United States)

^c AGILENT TECHNOLOGIES   (United States)

^d ADVANCED MICRO DEVICES   (United States)

^e PMC Sierra Inc   (United States)

Author keywords

CMOS integrated circuits; Dual path loop filter; Frequency synthesizers; Jitter; Phase locked loops; Serial links; Temperature sensitivity; Voltage controlled oscillators

Indexed keywords

DUAL-PATH LOOP FILTER; PHASE-LOCKED LOOPS; SERIAL LINKS; TEMPERATURE SENSITIVITY; VOLTAGE-CONTROLLED OSCILLATORS;

FREQUENCY SYNTHESIZERS; GAUSSIAN NOISE (ELECTRONIC); MOS DEVICES; PROGRAMMABLE LOGIC CONTROLLERS; TRANSMITTERS; TUNING; VARACTORS; VARIABLE FREQUENCY OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 33746924545     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.875289     Document Type: Conference Paper

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