A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 144-147

  Kim, Jaeha ^a   Kim, Jeong Kyoum ^a   Lee, Bong Joon ^a   Kim, Namhoon ^b   Jeong, Deog Kyoon ^a   Kim, Wonchan ^a  

^a Seoul National University   (South Korea)

^b Silicon Image Inc   (United States)

Author keywords

CMOS; Frequency divider; Phase locked loop; Pulsed latches; Reference spur; VCO optimization

Indexed keywords

ELECTRIC FILTERS; ELECTRIC INVERTERS; FREQUENCY DIVIDING CIRCUITS; JITTER; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; RESONATORS; TRANSMITTERS;

LOOP FILTERS; PULSED LATCHES; REFERENCE SPUR; VCO OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 33645687517     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469353     Document Type: Conference Paper

References (12)

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