-
1
-
-
0042708264
-
"The motor infrastructure: From ion channels to neuronal networks"
-
Jul
-
S. Grillner, "The motor infrastructure: From ion channels to neuronal networks," Nature Rev. Neurosci., vol. 4, pp. 573-586, Jul. 2003.
-
(2003)
Nature Rev. Neurosci.
, vol.4
, pp. 573-586
-
-
Grillner, S.1
-
2
-
-
0029894404
-
"A comparison of treadmill locomotion in adult cats before and after spinal transection"
-
M. Belanger, T. Drew, J. Provencher, and S. Rossignol, "A comparison of treadmill locomotion in adult cats before and after spinal transection," J. Neurophysiol., vol. 76, pp. 471-491, 1996.
-
(1996)
J. Neurophysiol.
, vol.76
, pp. 471-491
-
-
Belanger, M.1
Drew, T.2
Provencher, J.3
Rossignol, S.4
-
3
-
-
0021363144
-
"The effect of dorsal root transection on the efferent motor pattern in the cat's hindlimb during locomotion"
-
S. Grillner and P. Zangger, "The effect of dorsal root transection on the efferent motor pattern in the cat's hindlimb during locomotion," Acta Phys. Scand., vol. 120, pp. 393-405, 1984.
-
(1984)
Acta Phys. Scand.
, vol.120
, pp. 393-405
-
-
Grillner, S.1
Zangger, P.2
-
4
-
-
33746913555
-
"Locomotion"
-
in E. R. Kandel, J. H. Schwartz, and T. M. Jessell, Eds. New York: McGraw-Hill
-
K. Pearson and J. Gordon, "Locomotion," in Principles of Neural Science, E. R. Kandel, J. H. Schwartz, and T. M. Jessell, Eds. New York: McGraw-Hill, 2001.
-
(2001)
Principles of Neural Science
-
-
Pearson, K.1
Gordon, J.2
-
5
-
-
0027251798
-
"Nonlinear dynamics in a model neuron provide a novel mechanism for transient synaptic inputs to produce long-term alterations of postsynaptic activity"
-
C. C. Canavier, D. A. Baxter, J. W. Clark, and J. H. Byrne, "Nonlinear dynamics in a model neuron provide a novel mechanism for transient synaptic inputs to produce long-term alterations of postsynaptic activity," J. Neurophysiol., vol. 69, pp. 2252-2257, 1993.
-
(1993)
J. Neurophysiol.
, vol.69
, pp. 2252-2257
-
-
Canavier, C.C.1
Baxter, D.A.2
Clark, J.W.3
Byrne, J.H.4
-
6
-
-
1642553290
-
"Multimodal behavior in a four neuron ring circuit: Mode switching"
-
Feb
-
C. Luo, J. W. Clark, Jr., C. C. Canavier, D. A. Baxter, and J. H. Byrne, "Multimodal behavior in a four neuron ring circuit: Mode switching," IEEE Trans. Biomed. Eng., vol. 51, no. 2, pp. 205-218, Feb. 2004.
-
(2004)
IEEE Trans. Biomed. Eng.
, vol.51
, Issue.2
, pp. 205-218
-
-
Luo, C.1
Clark Jr., J.W.2
Canavier, C.C.3
Baxter, D.A.4
Byrne, J.H.5
-
7
-
-
0001331563
-
"Associative network models for central pattern generators"
-
in C. Koch and I. Segev, Eds. Cambridge, MA: MIT Press
-
D. Kleinfeld and H. Sompolinsky, "Associative network models for central pattern generators," in Methods in Neuronal Modeling, C. Koch and I. Segev, Eds. Cambridge, MA: MIT Press, 1989.
-
(1989)
Methods in Neuronal Modeling
-
-
Kleinfeld, D.1
Sompolinsky, H.2
-
8
-
-
0030283980
-
"Application of evolved locomotion controllers to a hexpod robot"
-
J. C. Gallagher, R. D. Beer, K. S. Espenschied, and R. D. Quinn, "Application of evolved locomotion controllers to a hexpod robot," Robot. Auton. Syst., vol. 19, pp. 95-103, 1996.
-
(1996)
Robot. Auton. Syst.
, vol.19
, pp. 95-103
-
-
Gallagher, J.C.1
Beer, R.D.2
Espenschied, K.S.3
Quinn, R.D.4
-
9
-
-
0031104227
-
"Biologically inspired approaches to robotics"
-
R. D. Beer, R. D. Quinn, H. J. Chiel, and R. E. Ritzmann, "Biologically inspired approaches to robotics," Commun. ACM, vol. 40, pp. 31-38, 1997.
-
(1997)
Commun. ACM
, vol.40
, pp. 31-38
-
-
Beer, R.D.1
Quinn, R.D.2
Chiel, H.J.3
Ritzmann, R.E.4
-
10
-
-
84898952414
-
"Analog VLSI model of intersegmental coordination with nearest-neighbor coupling"
-
G. N. Patel, J. H. Holleman, and S. P. DeWeerth, "Analog VLSI model of intersegmental coordination with nearest-neighbor coupling," Adv. Neural Inf. Process. Syst., vol. 11, pp. 719-725, 1998.
-
(1998)
Adv. Neural Inf. Process. Syst.
, vol.11
, pp. 719-725
-
-
Patel, G.N.1
Holleman, J.H.2
DeWeerth, S.P.3
-
11
-
-
0142129353
-
"Four-legged walking gait control using a neuromorphic chip interfaced to a support vector learning algorithm"
-
S. Still, B. Schölkopf, K. Hepp, and R. Douglas, "Four-legged walking gait control using a neuromorphic chip interfaced to a support vector learning algorithm," Adv. Neural Inf. Process. Syst., vol. 13, 2000.
-
(2000)
Adv. Neural Inf. Process. Syst.
, vol.13
-
-
Still, S.1
Schölkopf, B.2
Hepp, K.3
Douglas, R.4
-
12
-
-
0037586881
-
"An in silico central pattern generator: Silicon oscillator, coupling, entrainment, and physical computation"
-
M. A. Lewis, R. Etienne-Cummings, M. J. Hartmann, A. H. Cohen, and Z. R. Xu, "An in silico central pattern generator: Silicon oscillator, coupling, entrainment, and physical computation," Biol. Cybern., vol. 88, pp. 137-151, 2003.
-
(2003)
Biol. Cybern.
, vol.88
, pp. 137-151
-
-
Lewis, M.A.1
Etienne-Cummings, R.2
Hartmann, M.J.3
Cohen, A.H.4
Xu, Z.R.5
-
13
-
-
33746895503
-
"Entrainment of silicon central pattern generators for legged locomotory control"
-
F. Tenore, R. Etienne-Cummings, and M. A. Lewis, "Entrainment of silicon central pattern generators for legged locomotory control," Adv. Neural Inf. Process. Syst., vol. 16, 2003.
-
(2003)
Adv. Neural Inf. Process. Syst.
, vol.16
-
-
Tenore, F.1
Etienne-Cummings, R.2
Lewis, M.A.3
-
14
-
-
4344692605
-
"A programmable array of silicon neurons for the control of legged locomotion"
-
F. Tenore, R. Etienne-Cummings, and M. A. Lewis, "A programmable array of silicon neurons for the control of legged locomotion," in Proc. IEEE Int. Symp. Circuits Systems (ISCAS), 2004, vol. V, pp. 349-352.
-
(2004)
Proc. IEEE Int. Symp. Circuits Systems (ISCAS)
, vol.5
, pp. 349-352
-
-
Tenore, F.1
Etienne-Cummings, R.2
Lewis, M.A.3
-
15
-
-
84977060605
-
"On the dynamics of small continuous-time recurrent neural networks"
-
R. D. Beer, "On the dynamics of small continuous-time recurrent neural networks," Adapt. Behav., vol. 3, pp. 471-511, 1995.
-
(1995)
Adapt. Behav.
, vol.3
, pp. 471-511
-
-
Beer, R.D.1
-
16
-
-
0004469897
-
"Neurons with graded response properties have collective computational properties like those of two-state neurons"
-
J. J. Hopfield, "Neurons with graded response properties have collective computational properties like those of two-state neurons," Proc. Nat. Acad. Sciences, vol. 81, pp. 3088-3092, 1984.
-
(1984)
Proc. Nat. Acad. Sciences
, vol.81
, pp. 3088-3092
-
-
Hopfield, J.J.1
-
17
-
-
0027154319
-
"Approximation of dynamical systems by continuous time recurrent neural networks"
-
K. Funahashi and Y. Nakamura, "Approximation of dynamical systems by continuous time recurrent neural networks," Neural Netw., vol. 6, pp. 801-806, 1993.
-
(1993)
Neural Netw.
, vol.6
, pp. 801-806
-
-
Funahashi, K.1
Nakamura, Y.2
-
19
-
-
0026384824
-
"An analog neural network processor with programmable topology"
-
Dec
-
B. E. Boser, E. Sackinger, J. Bromley, Y. L. Cun, and L. D. Jackel, "An analog neural network processor with programmable topology," IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 2017-2025, Dec. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, Issue.12
, pp. 2017-2025
-
-
Boser, B.E.1
Sackinger, E.2
Bromley, J.3
Cun, Y.L.4
Jackel, L.D.5
-
20
-
-
0026727537
-
"A reconfigurable VLSI neural network"
-
Jan
-
S. Satyanarayana, Y. P. Tsividis, and H. P. Graf, "A reconfigurable VLSI neural network," IEEE J. Solid-State Circuits, vol. 27, no. 1, pp. 67-81, Jan. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.1
, pp. 67-81
-
-
Satyanarayana, S.1
Tsividis, Y.P.2
Graf, H.P.3
-
21
-
-
0031095256
-
"Toward a general-purpose analog VLSI neural network with on-chip learning"
-
Mar
-
A. J. Montalvo, R. S. Gyurcsik, and J. J. Paulos, "Toward a general-purpose analog VLSI neural network with on-chip learning," IEEE Trans. Neural Netw., vol. 8, no. 2, pp. 413-423, Mar. 1997.
-
(1997)
IEEE Trans. Neural Netw.
, vol.8
, Issue.2
, pp. 413-423
-
-
Montalvo, A.J.1
Gyurcsik, R.S.2
Paulos, J.J.3
-
22
-
-
0030106428
-
"An analog VLSI recurrent neural network learning a continuous-time trajectory"
-
Mar
-
G. Cauwenburghs, "An analog VLSI recurrent neural network learning a continuous-time trajectory," IEEE Trans. Neural Netw., vol. 7, no. 2, pp. 346-361, Mar. 1997.
-
(1997)
IEEE Trans. Neural Netw.
, vol.7
, Issue.2
, pp. 346-361
-
-
Cauwenburghs, G.1
-
23
-
-
0026172110
-
"Analog floating-gate synapses for general-purpose VLSI neural computation"
-
Jun
-
B. W. Lee, B. J. Sheu, and H. Yang, "Analog floating-gate synapses for general-purpose VLSI neural computation," IEEE Trans. Circuits Syst., vol. 38, no. 6, pp. 654-658, Jun. 1991.
-
(1991)
IEEE Trans. Circuits Syst.
, vol.38
, Issue.6
, pp. 654-658
-
-
Lee, B.W.1
Sheu, B.J.2
Yang, H.3
-
24
-
-
0027555961
-
"Design and characterization analog VLSI neural network modules"
-
Mar
-
S. M. Gowda, B. J. Sheu, J. Choi, C. G. Hwang, and J. S. Cable, "Design and characterization analog VLSI neural network modules," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 301-313, Mar. 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, Issue.3
, pp. 301-313
-
-
Gowda, S.M.1
Sheu, B.J.2
Choi, J.3
Hwang, C.G.4
Cable, J.S.5
-
25
-
-
0035051734
-
"Continuous-time feedback in floating-gate CMOS circuits"
-
Jan
-
P. Hasler, "Continuous-time feedback in floating-gate CMOS circuits," IEEE Trans. Circuits Syst. II, vol. 48, no. 1, pp. 56-64, Jan. 2001.
-
(2001)
IEEE Trans. Circuits Syst. II
, vol.48
, Issue.1
, pp. 56-64
-
-
Hasler, P.1
-
26
-
-
0033874491
-
"A p-channel MOS synapse transistor with self-convergent memory writes"
-
Feb
-
C. Diorio, "A p-channel MOS synapse transistor with self-convergent memory writes," IEEE Trans. Electron Devices, vol. 47, no. 2, pp. 464-472, Feb. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.2
, pp. 464-472
-
-
Diorio, C.1
-
27
-
-
0034464977
-
"A continuously-adapting analog node using floating-gate synapses"
-
J. Dugger and P. Hasler, "A continuously-adapting analog node using floating-gate synapses," in Proc. 43rd IEEE Midwest Symp. Circuits Systems, 2000, pp. 1058-1061.
-
Proc. 43rd IEEE Midwest Symp. Circuits Systems
, vol.2000
, pp. 1058-1061
-
-
Dugger, J.1
Hasler, P.2
-
28
-
-
0006772020
-
"Digital-analog hybrid synapse chips for electronic neural networks"
-
A. Moopenn, T. Duong, and A. P. Thakoor, "Digital-analog hybrid synapse chips for electronic neural networks," Adv. Neural Inf. Process. Syst., vol. 2, pp. 769-776, 1990.
-
(1990)
Adv. Neural Inf. Process. Syst.
, vol.2
, pp. 769-776
-
-
Moopenn, A.1
Duong, T.2
Thakoor, A.P.3
-
29
-
-
0029707929
-
"Design and VLSI implementation of a unified neuron-synapse architecture"
-
H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, "Design and VLSI implementation of a unified neuron-synapse architecture," in Proc. 6th Great Lakes Symp. VLSI, 1996, pp. 228-233.
-
(1996)
Proc. 6th Great Lakes Symp. VLSI
, pp. 228-233
-
-
Djahanshahi, H.1
Ahmadi, M.2
Jullien, G.A.3
Miller, W.C.4
-
30
-
-
0242443320
-
"Compact low-power calibration mini-DACs for neural arrays with programmable weights"
-
Sep
-
B. Linares-Barranco, T. Serrano-Gotarredona, and R. Serrano-Gotarredona, "Compact low-power calibration mini-DACs for neural arrays with programmable weights," IEEE Trans. Neural Netw., vol. 14, no. 5, pp. 1207-1216, Sep. 2003.
-
(2003)
IEEE Trans. Neural Netw.
, vol.14
, Issue.5
, pp. 1207-1216
-
-
Linares-Barranco, B.1
Serrano-Gotarredona, T.2
Serrano-Gotarredona, R.3
-
31
-
-
4344650976
-
"An MDAC synapse for analog neural networks"
-
R. J. Kier, R. R. Harrison, and R. D. Beer, "An MDAC synapse for analog neural networks," in Proc. IEEE Int. Symp. Circuits Systems (ISCAS), 2004, vol. V, pp. 752-755.
-
(2004)
Proc. IEEE Int. Symp. Circuits Systems (ISCAS)
, vol.5
, pp. 752-755
-
-
Kier, R.J.1
Harrison, R.R.2
Beer, R.D.3
-
32
-
-
33746890918
-
"Design of pattern generators in analog integrated circuits"
-
master's thesis, Univ. Utah, Aug
-
R. J. Kier, "Design of pattern generators in analog integrated circuits," master's thesis, Univ. Utah, Aug. 2004.
-
(2004)
-
-
Kier, R.J.1
-
33
-
-
0026987730
-
"An inherently linear and compact MOST-only current division technique"
-
Dec
-
K. Bult and G. J. G. M. Geelen, "An inherently linear and compact MOST-only current division technique," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1730-1735, Dec. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.12
, pp. 1730-1735
-
-
Bult, K.1
Geelen, G.J.G.M.2
-
34
-
-
0027908310
-
"Linear networks based on transistors"
-
E. A. Vittoz and X. Arreguit, "Linear networks based on transistors," Electron. Lett., vol. 20, pp. 297-299, 1993.
-
(1993)
Electron. Lett.
, vol.20
, pp. 297-299
-
-
Vittoz, E.A.1
Arreguit, X.2
-
35
-
-
0026866715
-
"Improved implementations of the silicon cochlea"
-
May
-
L. Watts, D. A. Kerns, R. F. Lyon, and C. A. Mead, "Improved implementations of the silicon cochlea," IEEE J. Solid-State Circuits, vol. 27, no. 5, pp. 692-700, May 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.5
, pp. 692-700
-
-
Watts, L.1
Kerns, D.A.2
Lyon, R.F.3
Mead, C.A.4
-
36
-
-
0004230021
-
"Efficient precise computation with noisy components extrapolating from an electronic cochlea to the brain"
-
Ph.D. dissertation, California Inst. Tech., Pasadena, CA
-
R. Sarpeshkar, "Efficient precise computation with noisy components extrapolating from an electronic cochlea to the brain," Ph.D. dissertation, California Inst. Tech., Pasadena, CA, 1997.
-
(1997)
-
-
Sarpeshkar, R.1
-
39
-
-
33645723390
-
"Design methods for pattern generation circuits"
-
M.S. thesis, Case Western Reserve Univ., Cleveland, OH
-
J. C. Ames, "Design methods for pattern generation circuits," M.S. thesis, Case Western Reserve Univ., Cleveland, OH, 2003.
-
(2003)
-
-
Ames, J.C.1
|