Design and VLSI implementation of a unified synapse-neuron architecture

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 228-233

  Djahanshahi, H ^a   Ahmadi, M ^a   Jullien, G A ^a   Miller, W C ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

EFFICIENCY; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MOSFET DEVICES; NEURAL NETWORKS; PRINTED CIRCUIT DESIGN; ROBUSTNESS (CONTROL SYSTEMS);

SYNAPSE-NEURON ARCHITECTURE;

VLSI CIRCUITS;

EID: 0029707929     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)