-
1
-
-
84944392430
-
Checkpoint processing and recovery: Towards scalable large instruction window processors
-
San Diego, CA, USA, May
-
H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. In Proceedings of the 36th International Symposium on Microarchitecture, pages 423-434, San Diego, CA, USA, May 2003.
-
(2003)
Proceedings of the 36th International Symposium on Microarchitecture
, pp. 423-434
-
-
Akkary, H.1
Rajwar, R.2
Srinivasan, S.T.3
-
2
-
-
0036469652
-
SimpleScalar: An infrastructure for computer system modeling
-
February
-
T. Austin, E. Larson, and D. Ernst. SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Micro Magazine, pages 59-67, February 2002.
-
(2002)
IEEE Micro Magazine
, pp. 59-67
-
-
Austin, T.1
Larson, E.2
Ernst, D.3
-
3
-
-
84988438049
-
Toward kilo-instruction processors
-
December
-
A. Cristal, O. J. Santana, M. Valero, and J. F. Martínez. Toward Kilo-Instruction Processors. Transactions on Architecture and Code Optimization, 1(4):389-417, December 2004.
-
(2004)
Transactions on Architecture and Code Optimization
, vol.1
, Issue.4
, pp. 389-417
-
-
Cristal, A.1
Santana, O.J.2
Valero, M.3
Martínez, J.F.4
-
5
-
-
2342591856
-
The intel pentium M processor: Microarchitecture and performance
-
May
-
S. Gochtnan, R. Ronen, I. Anati, A. Berkovitz, T. Kurts, A. Naveh, A. Saeed, Z. Sperber, and R. C. Valentine. The Intel Pentium M Processor: Microarchitecture and Performance. Intel Technology Journal, 7(2), May 2003.
-
(2003)
Intel Technology Journal
, vol.7
, Issue.2
-
-
Gochtnan, S.1
Ronen, R.2
Anati, I.3
Berkovitz, A.4
Kurts, T.5
Naveh, A.6
Saeed, A.7
Sperber, Z.8
Valentine, R.C.9
-
7
-
-
84944408863
-
Fast path-based neural branch prediction
-
San Diego, CA, USA, December
-
D. A. Jiménez. Fast Path-Based Neural Branch Prediction. In Proceedings of the 36th International Symposium on Microarchitecture, pages 243-252, San Diego, CA, USA, December 2003.
-
(2003)
Proceedings of the 36th International Symposium on Microarchitecture
, pp. 243-252
-
-
Jiménez, D.A.1
-
8
-
-
71049193515
-
Reconsidering complex branch predictors
-
Anaheim, CA, USA, February
-
D. A. Jiménez. Reconsidering Complex Branch Predictors. In Proceedings of the 9th International Symposium on High Performance Computer Architecture, pages 43-52, Anaheim, CA, USA, February 2003.
-
(2003)
Proceedings of the 9th International Symposium on High Performance Computer Architecture
, pp. 43-52
-
-
Jiménez, D.A.1
-
10
-
-
0034462654
-
The impact of delay on the design of branch predictors
-
Monterey, CA, USA, December
-
D. A. Jiménez, S. W. Keckler, and C. Lin. The Impact of Delay on the Design of Branch Predictors. In Proceedings of the 33rd International Symposium on Microarchitecture, pages 4-13, Monterey, CA, USA, December 2000.
-
(2000)
Proceedings of the 33rd International Symposium on Microarchitecture
, pp. 4-13
-
-
Jiménez, D.A.1
Keckler, S.W.2
Lin, C.3
-
11
-
-
1942512699
-
Neural methods for dynamic branch prediction
-
November
-
D. A. Jiménez and C. Lin. Neural Methods for Dynamic Branch Prediction. ACM Transactions on Computer Systems, 20(4):369-397, November 2002.
-
(2002)
ACM Transactions on Computer Systems
, vol.20
, Issue.4
, pp. 369-397
-
-
Jiménez, D.A.1
Lin, C.2
-
12
-
-
84962163449
-
MASE: A novel infrastructure for detailed microarchitectural modeling
-
Tucson, AZ, USA, November
-
E. Larson, S. Chatterjee, and T. Austin. MASE: A Novel Infrastructure for Detailed Microarchitectural Modeling. In Proceedings of the 2001 International Symposium on Performance Analysis of Systems and Software, pages 1-9, Tucson, AZ, USA, November 2001.
-
(2001)
Proceedings of the 2001 International Symposium on Performance Analysis of Systems and Software
, pp. 1-9
-
-
Larson, E.1
Chatterjee, S.2
Austin, T.3
-
13
-
-
0031338573
-
The BiMode branch predictor
-
Research Triangle Park, NC, USA, December
-
C.-C. Lee, I.-C. K. Chen, and T. N. Mudge. The BiMode Branch Predictor. In Proceedings of the 30th International Symposium on Microarchitecture, pages 4-13, Research Triangle Park, NC, USA, December 1997.
-
(1997)
Proceedings of the 30th International Symposium on Microarchitecture
, pp. 4-13
-
-
Lee, C.-C.1
Chen, I.-C.K.2
Mudge, T.N.3
-
15
-
-
33746694178
-
Reducing the power and complexity of path-based neural branch prediction
-
Madison, WI, USA, June
-
G. H. Loh and D. A. Jiménez. Reducing the Power and Complexity of Path-Based Neural Branch Prediction. In Proceedings of the 5th Workshop on Complexity-Effective Design, pages 1-8, Madison, WI, USA, June 2005.
-
(2005)
Proceedings of the 5th Workshop on Complexity-effective Design
, pp. 1-8
-
-
Loh, G.H.1
Jiménez, D.A.2
-
16
-
-
0003506711
-
-
TN 36, Compaq Computer Corporation Western Research Laboratory, June
-
S. McFarling. Combining Branch Predictors. TN 36, Compaq Computer Corporation Western Research Laboratory, June 1993.
-
(1993)
Combining Branch Predictors
-
-
McFarling, S.1
-
18
-
-
0030645118
-
Trading conflict and capacity aliasing in conditional branch predictors
-
Boulder, CO, USA, June
-
P. Michaud, A. Seznec, and R. Uhlig. Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. In Proceedings of the 24th International Symposium on Computer Architecture, pages 292-303, Boulder, CO, USA, June 1997.
-
(1997)
Proceedings of the 24th International Symposium on Computer Architecture
, pp. 292-303
-
-
Michaud, P.1
Seznec, A.2
Uhlig, R.3
-
19
-
-
84968756972
-
Picking statistically valid and early simulation points
-
New Orleans, LA, USA, September
-
E. Perelman, G. Hamerly, and B. Calder. Picking Statistically Valid and Early Simulation Points. In Proceedings of the 2003 International Conference on Parallel Architectures and Compilation Techniques, pages 244-255, New Orleans, LA, USA, September 2004.
-
(2004)
Proceedings of the 2003 International Conference on Parallel Architectures and Compilation Techniques
, pp. 244-255
-
-
Perelman, E.1
Hamerly, G.2
Calder, B.3
-
21
-
-
0036290739
-
Design tradeoffs for the alpha EV8 conditional branch predictor
-
Anchorage, AK, USA, May
-
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. In Proceedings of the 29th International Symposium on Computer Architecture, Anchorage, AK, USA, May 2002.
-
(2002)
Proceedings of the 29th International Symposium on Computer Architecture
-
-
Seznec, A.1
Felix, S.2
Krishnan, V.3
Sazeides, Y.4
-
24
-
-
0019893647
-
A study of branch prediction strategies
-
Minneapolis, MN, USA, May
-
J. E. Smith. A Study of Branch Prediction Strategies. In Proceedings of the 8th International Symposium on Computer Architecture, pages 135-148, Minneapolis, MN, USA, May 1981.
-
(1981)
Proceedings of the 8th International Symposium on Computer Architecture
, pp. 135-148
-
-
Smith, J.E.1
-
25
-
-
0036296819
-
Increasing processor performance by implementing deeper pipelines
-
Anchorage, AK, USA, May
-
E. Sprangle and D. Carmean. Increasing Processor Performance by Implementing Deeper Pipelines. In Proceedings of the 29th International Symposium on Computer Architecture, pages 25-34, Anchorage, AK, USA, May 2002.
-
(2002)
Proceedings of the 29th International Symposium on Computer Architecture
, pp. 25-34
-
-
Sprangle, E.1
Carmean, D.2
-
26
-
-
12844269176
-
Continual flow pipelines
-
Boston, MA, USA, October
-
S. T. Srinivasan, R. Rajwar, H. Akkary, A. Gandhi, and M. Upton. Continual Flow Pipelines. In Proceedings of the 11th Symposium on Architectural Support for Programming Languages and Operating Systems, pages 107-119, Boston, MA, USA, October 2004.
-
(2004)
Proceedings of the 11th Symposium on Architectural Support for Programming Languages and Operating Systems
, pp. 107-119
-
-
Srinivasan, S.T.1
Rajwar, R.2
Akkary, H.3
Gandhi, A.4
Upton, M.5
-
27
-
-
0029192697
-
Cache design trade-offs for power and performance optimization: A case study
-
Dana Point, CA, USA, April
-
C.-L. Su and A. M. Despain. Cache Design Trade-offs for Power and Performance Optimization: A Case Study. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 63-68, Dana Point, CA, USA, April 1995.
-
(1995)
Proceedings of the International Symposium on Low Power Electronics and Design
, pp. 63-68
-
-
Su, C.-L.1
Despain, A.M.2
-
30
-
-
0038346222
-
Improving branch prediction by dynamic dataflow-based identification of correlated branches from a large global history
-
San Diego, CA, USA, May
-
R. Thomas, M. Franklin, C. Wilkerson, and J. Stark. Improving Branch Prediction by Dynamic Dataflow-based Identification of Correlated Branches from a Large Global History. In Proceedings of the 30th International Symposium on Computer Architecture, pages 314-323, San Diego, CA, USA, May 2003.
-
(2003)
Proceedings of the 30th International Symposium on Computer Architecture
, pp. 314-323
-
-
Thomas, R.1
Franklin, M.2
Wilkerson, C.3
Stark, J.4
|