Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

IEEE Electron Device Letters

Volumn 27, Issue 8, 2006, Pages 659-661

  Lin, Hong Nien ^a   Chen, Hung Wei ^b   Ko, Chih Hsin ^b   Ge, Chung Hu ^b   Lin, Horng Chih ^a   Huang, Tiao Yuan ^a   Lee, Wen Chin ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

CMOSFETs; Current; Mobility; Strain

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRON MOBILITY; NANOTECHNOLOGY; STRAIN;

DRAIN-CURRENT GAIN; NANOSCALE STRAINED CMOS; NANOSCALE STRAINED MOSFET; STRAIN-INDUCED MOBILITY;

MOSFET DEVICES;

EID: 33746556858     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.878035     Document Type: Article

References (9)

1. T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. Mclntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, "A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors," in IEDM Tech. Dig., 2003, pp. 978-980.
2. S. E. Thompson, R. S. Chau, T. Ghani, K. Mistry, S. Tyagi, andM. T. Bohr, "In search of 'forever,' continued transistor scaling one new material at a time," IEEE Trans. Semicond. Manuf., vol. 18, no. 1, pp. 26-36, Feb. 2005.
3. H.-N. Lin, H.-W. Chen, C.-H. Ko, C.-H. Ge, H.-C. Lin, T.-Y. Huang, W.-C. Lee, and D. D. Tang, "The impact of uniaxial strain engineering on channel backscattering in nanoscale MOSFETs," in VLSI Symp. Tech. Dig., 2005, pp. 174-175.
4. C.-H. Ge, C.-C. Lin, C.-H. Ko, C.-C. Huang, Y.-C. Huang, B.-W. Chan, B.-C. Perng, C.-C. Sheu, P.-Y. Tasi, L.-G. Yao, C.-L. Wu, T.-L. Lee, C.-J. Chen, C.-T. Wang, S.-C. Lin, Y.-C. Yeo, and C. Hu, "Process-strained Si (PSS) CMOS technology featuring 3D strain engineering," in IEDM Tech. Dig., 2003, pp. 73-76.
5. M. S. Lundstrom, "On the mobility versus drain-current relation for a nanoscale MOSFET," IEEE Electron Device Lett., vol. 22, no. 6, pp. 293-295, Jun. 2001.
6. P. R. Chidambaram, B. A. Smith, L. H. Hall, H. Bu, S. Chakravarthi, Y. Kim, A. V. Samoilov, A. T. Kim, P. J. Jones, R. B. Irwin, M. J. Kim, A. L. P. Rotondaro, C. F. Machala, and D. T. Grider, "35% drive current improvement from recessed SiGe drain extensions on 37 nm gate length PMOS," in VLSI Symp. Tech. Dig., 2004, pp. 48-49.
7. T. Sanuki, A. Oishi, Y. Morimasa, S. Aota, T. Kinoshita, R. Hasumi, Y. Takegawa, K. Isobe, H. Yoshimura, M. Iwai, K. Sunouchi, and T. Noguchi, "Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology," in IEDM Tech. Dig., 2003, pp. 65-68.
8. S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffmann, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B.Mcintyre, K.Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, "A 90-nm logic technology featuring strained-silicon," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004.
9. H.-N. Lin, H.-W. Chen, C.-H. Ko, C.-H. Ge, H.-C. Lin, T.-Y. Huang, and W.-C. Lee, "Channel backscattering characteristics of strained pMOSFETs with embedded SiGe source/drain," in IEDM Tech. Dig., 2005, pp. 147-150.