Effect of the prefabricated routing track distribution on FPGA area-efficiency

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 3, 1998, Pages 445-456

  Betz, Vaughn ^a,b   Rose, Jonathan ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

Author keywords

Circuit global routing; Circuit placement; Design automation; Field programmable gate array architecture; Field programmable gate arrays

Indexed keywords

ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; ROUTERS;

CIRCUIT GLOBAL ROUTING; ROUTING TRACK DISTRIBUTIONS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032162979     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.711315     Document Type: Article

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