Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

VLSI Design

Volumn 4, Issue 4, 1996, Pages 275-291

  Brown, Stephen ^a   Khellah, Muhammad ^a   Lemieux, Guy ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

CAD; Field programmable Gate Arrays; FPGAs; Routability; Speed performance

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS; ROUTABILITY; ROUTING;

LOGIC GATES;

EID: 0029701861     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1996/45983     Document Type: Article

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