Statistical clock tree routing for robustness to process variations

Proceedings of the International Symposium on Physical Design

Volumn 2006, Issue , 2006, Pages 149-156

  Padmanabhan, Uday ^a   Wang, Janet M ^a   Hu, Jiang ^b  

^a University of Arizona   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Clock Tree; Process Variations; Robustness; Routing

Indexed keywords

ALGORITHMS; ROBUSTNESS (CONTROL SYSTEMS); ROUTERS; STATISTICAL MECHANICS;

CLOCK TREE; PROCESS VARIATIONS; ROUTING;

TREES (MATHEMATICS);

EID: 33745933646     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1123008.1123037     Document Type: Conference Paper

References (19)

1. R.-S. Tsay, "Exact Zero Skew", ICCAD, pp. 336-339, 1991.
2. T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength", IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. CAS-39, No. 11, pp. 799-814, Nov. 1992.
3. M. Edahiro, "A Clustering-Based Optimization Algorithm in Zero-Skew Routings", DAC 1993, pp. 612-616, 1993.
4. J. G. Xi, and W. W.-M. Dai, "Useful-Skew Clock Routing with Gate Sizing for Low Power Design", DAC, pp. 383-388, 1996.
5. J. Cong, A. B. Kahng, C.-K. Koh, and C.-W. A. Tsao, "Bounded-Skew Clock and Steiner Routing under Elmore Delay", ICCAD, pp. 66-71, 1995.
6. Y. Liu, S. Nassif, L. Pileggi, and A. Strojwas, "Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor", DAC, pp. 168-171, 2000.
7. S. Pullela, N. Menezes, and L. T. Pillage, "Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization", DAC, pp. 165-170, 1993.
8. B. Lu, J. Hu, G. Ellis, and H. Su, "Process Variation Aware Clock Tree Routing", ISPD, pp. 174-181, 2003.
9. G. Venkataraman, C. N. Sze, and J. Hu, "Skew Scheduling and Clock Routing for Improved Tolerance to Process Variations", ASP-DAC, 594-599, 2005.
10. W. D. Lam and C.-K. Koh, "Process Variation Robust Clock Tree Routing," ASP-DAC, pp. 606-611, 2005.
11. A. I. Abou-Seido, B. Nowak, and C. Chu, "Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 7, July 2004.
12. D. C. Montgomery, Design and Analysis of Experiments, John Wiley and Sons, 1997.
13. I. S. Kourtev and E. G. Friedman, "Clock skew scheduling for improved reliability via quadratic programming," ICCAD, pp. 239-243, 1999.
14. V. Mehrotra, "Modeling the Effects of Systematic Process Variation on Circuit Performance", PhD Dissertation, MIT.
15. H. Chang, V. Zolotoy, S. Narayan and C. Visweswariah, "Parameterized Block-Based Statistical Timing Analysis with Non-Gaussian Parameters, Nonlinear Delay Functions", DAC, pp. 71-76, 2005.
16. L. Zhang, W. Chen, Y. Hu, J. Gubner, and C. C-P. Chen, "Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model", DAC, pp. 83-88, 2005.
17. A. Papoulis and S. U. Pillai, Probability, Random Variables and Stochastic Processes, McGraw-Hill, Fourth Edition, 2002.
18. F. Liu, C. Kashyap, and C. J. Alpert, "A Delay Metric for RC Circuits Based on the Weibull Distribution", ICCAD, pp. 620-624, 2002.
19. H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," ICCAD, pp. 621-625, 2003.