Automatic transistor and physical design of FPGA tiles from an architectural specification

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 164-172

  Padalia, Ketan ^a   Fung, Ryan ^a   Bourgeault, Mark ^a   Egier, Aaron ^a   Rose, Jonathan ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Automatic layout; FPGA; PLD; Programmable logic

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; ROUTERS; SCHEMATIC DIAGRAMS;

AUTOMATIC TRANSISTOR; GOOD INSTANT LAYOUT OF ERASABLE SEMICONDUCTORS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038005995     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611817.611842     Document Type: Conference Paper

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