Optimal implementation of sea of leads (SoL) compliant interconnect technology

Proceedings of the IEEE 2004 International Interconnect Technology Conference

Volumn , Issue , 2004, Pages 99-101

  Dang, Bing ^a   Patel, Chirag ^b   Thacker, Hiren ^a   Bakir, Muhannad ^a   Martin, Kevin ^a   Meindl, James ^a,b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTERNATIONAL TECHNOLOGY ROADMAP OF SEMICONDUCTOR (ITRS); SEA OF LEADS (SOL) TECHNOLOGY; WAFER LEVEL PACKAGES; WET ETCHING;

DELAMINATION; DIELECTRIC MATERIALS; DRY ETCHING; ELECTROPLATED PRODUCTS; INPUT OUTPUT PROGRAMS; INTERFACES (MATERIALS); INTERMETALLICS; MICROPROCESSOR CHIPS; PASSIVATION; PHOTOLITHOGRAPHY; SOLDERED JOINTS; STRAIN; WSI CIRCUITS;

OPTICAL INTERCONNECTS;

EID: 8644238219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. International Technology Roadmap of Semiconductor, 2002.
2. Q. Zhu, L. Ma and S. K. Sitaraman, "β-Helix: A lithography-Based Compliant Off-Chip Interconnect," IEEE Transactions on Components and Packaging Technologies, vol.26, no.3, pp.582-590, 2003.
3. V. Solberg, D. Light and J. Fjelstad, "Reliable and Low Cost Wafer Level Packaging," IEEE/CPMT Int'l Electronics Manufacturing Technology Symposium, pp. 108-114, 2000.
4. Q. Zhu, L. Ma and S. K. Sitaraman, "Design Optimization of OneTurn Helix: A Novel Compliant Off-chip Interconnect," IEEE Transactions on Advanced Packaging, vol.26, no.2, pp.106-112, 2002.
5. M.S. Bakir, H.A. Reed, H.D. Thacker, C.S. Patel, P.A. Kohl, K.P. Martin, and J.D Meindl, "Sea of Leads (SoL) Ultrahigh Density Wafer-Level Chip Input/Output Interconnections for Gigascale Integration (GSI)," IEEE Transactions on Electron Devices, vol.50, no.10, pp.2039-2048, 2003.
6. C.S. Patel, "Compliant Wafer Level Packaging Technology," Ph.D Thesis, Georgia Institute of Technology, 2001.
7. M.S. Bakir, "Sea of Leads Electrical-Optical Polymer Pillar Chip I/O Interconnections For Gigascale Integration," Ph.D Thesis, Georgia Institute of Technology, August 2003.
8. S.Y. Jang and K.W. Paik, "Comparison of Electroplated Eutectic Bi/Sn and Pb/Sn Solder Bumps on Various UBM Systems," IEEE Transactions Electronics Packaging Manufacturing, vol.24, no.4, pp. 269-274, 2001.
9. K.C. Chan, Z.W. Zhong, K.W. Ong, "Investigation of Cr/Cu/Cu/Ni Under Bump Metallization for Lead-free Applications," 4th Electronics Packaging Technology Conference, Dec 10-12, pp. 270 275, 2002.