-
1
-
-
33744735090
-
-
The International Technology Roadmap for Semiconductor (ITRS) San Jose, CA
-
The International Technology Roadmap for Semiconductor (ITRS), 2003, San Jose, CA.
-
(2003)
-
-
-
2
-
-
33744770733
-
"Sub-20 nm CMOS FinFET technologies"
-
Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "Sub-20 nm CMOS FinFET technologies," in IEDM Tech. Dig., 2000, pp. 719-722.
-
(2000)
IEDM Tech. Dig.
, pp. 719-722
-
-
Choi, Y.-K.1
Lindert, N.2
Xuan, P.3
Tang, S.4
Ha, D.5
Anderson, E.6
King, T.-J.7
Bokor, J.8
Hu, C.9
-
3
-
-
29044440093
-
"FinFET - A self-aligned double-gate MOSFET scalable to 20 nm"
-
Dec
-
D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Boker, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.-J.8
Boker, J.9
Hu, C.10
-
4
-
-
0842331400
-
"Reliability study of CMOS FinFETs"
-
Y.-K. Choi, D. Ha, E. Snow, J. Bokor, and T.-J. King, "Reliability study of CMOS FinFETs," in IEDM Tech. Dig., 2003, pp. 177-180.
-
(2003)
IEDM Tech. Dig.
, pp. 177-180
-
-
Choi, Y.-K.1
Ha, D.2
Snow, E.3
Bokor, J.4
King, T.-J.5
-
5
-
-
20544449943
-
"Hot-carrier effects in p-channel modified Schottky-barrier FinFETs"
-
Jun
-
C.-P. Lin and B.-Y. Tsui, "Hot-carrier effects in p-channel modified Schottky-barrier FinFETs," IEEE Electron Device Lett., vol. 26, no. 6, pp. 394-396, Jun. 2005.
-
(2005)
IEEE Electron Device Lett.
, vol.26
, Issue.6
, pp. 394-396
-
-
Lin, C.-P.1
Tsui, B.-Y.2
-
6
-
-
28744443129
-
Fin = 20 ∼ 70 nm)"
-
Fin = 20 ∼ 70 nm)," in Proc. 43rd Annu. Reliab. Phys. Symp., 2005, pp. 352-355.
-
(2005)
Proc. 43rd Annu. Reliab. Phys. Symp.
, pp. 352-355
-
-
Ahn, Y.J.1
Cho, H.J.2
Kang, H.S.3
Lee, C.-H.4
Lee, C.5
Yoon, J.-M.6
Kim, T.Y.7
Cho, E.S.8
Sung, S.-K.9
Park, D.10
Kim, K.11
Ryu, B.-I.12
-
7
-
-
23844461114
-
"Hot carrier-induced degradation in bulk FinFETs"
-
Aug
-
S.-Y. Kim and J. H. Lee, "Hot carrier-induced degradation in bulk FinFETs," IEEE Electron Device Lett., vol. 26, no. 8, pp. 266-568, Aug. 2005.
-
(2005)
IEEE Electron Device Lett.
, vol.26
, Issue.8
, pp. 266-568
-
-
Kim, S.-Y.1
Lee, J.H.2
-
8
-
-
0037480885
-
"Extension and source/drain design for high-performance FinFET devices"
-
Apr
-
J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H.-S. P.Wong, "Extension and source/drain design for high-performance FinFET devices," IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 952-958, Apr. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.4
, pp. 952-958
-
-
Kedzierski, J.1
Ieong, M.2
Nowak, E.3
Kanarsky, T.S.4
Zhang, Y.5
Roy, R.6
Boyd, D.7
Fried, D.8
Wong, H.-S.P.9
-
9
-
-
0141761522
-
"Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers"
-
T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, "Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers," in VLSI Symp. Tech. Dig., 2003, pp. 135-136.
-
(2003)
VLSI Symp. Tech. Dig.
, pp. 135-136
-
-
Park, T.1
Choi, S.2
Lee, D.H.3
Yoo, J.R.4
Lee, B.C.5
Kim, J.Y.6
Lee, C.G.7
Chi, K.K.8
Hong, S.H.9
Hyun, S.J.10
Shin, Y.G.11
Han, J.N.12
Park, I.S.13
Chung, U.I.14
Moon, J.T.15
Yoon, E.16
Lee, J.H.17
-
10
-
-
0032099279
-
"Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFET's"
-
Jun
-
S. Biesemans, M. Hendriks, S. Kubicek, and K. D. Meyer, "Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFET's," IEEE Trans. Electron Devices, vol. 45, no. 6, pp. 1310-1316, Jun. 1998.
-
(1998)
IEEE Trans. Electron Devices
, vol.45
, Issue.6
, pp. 1310-1316
-
-
Biesemans, S.1
Hendriks, M.2
Kubicek, S.3
Meyer, K.D.4
-
11
-
-
33744764666
-
"Optimization of layout and doping profile design for BT(bodytied)-FinFET DRAM"
-
C.-H. Lee, C. Lee, J. Yoon, K. Kim, S. B. Park, H. S. Kang, Y. J. Ahn, and D. Park, "Optimization of layout and doping profile design for BT(bodytied)-FinFET DRAM," in Proc. SSDM Int. Conf., 2005, pp. 185-186.
-
(2005)
Proc. SSDM Int. Conf.
, pp. 185-186
-
-
Lee, C.-H.1
Lee, C.2
Yoon, J.3
Kim, K.4
Park, S.B.5
Kang, H.S.6
Ahn, Y.J.7
Park, D.8
-
12
-
-
0023438606
-
"Hot-electron effects in silicon-on-insulator n-channel MOSFET's"
-
ED-34 Oct
-
J.-P. Colinge, "Hot-electron effects in silicon-on-insulator n-channel MOSFET's," IEEE Trans. Electron Devices, vol. ED-34, no. 10, pp. 2173-2177, Oct. 1987.
-
(1987)
IEEE Trans. Electron Devices
, Issue.10
, pp. 2173-2177
-
-
Colinge, J.-P.1
-
13
-
-
0020952509
-
"Hot-electron effects in MOSFET's"
-
C. Hu, "Hot-electron effects in MOSFET's," in IEDM Tech. Dig., 1983, pp. 176-181.
-
(1983)
IEDM Tech. Dig.
, pp. 176-181
-
-
Hu, C.1
-
14
-
-
0021601456
-
"A simple method to characterize substrate current in MOSFET's"
-
EDL-5 Dec
-
T. Y. Chan, P. K. Ko, and C. Hu, "A simple method to characterize substrate current in MOSFET's," IEEE Electron Device Lett., vol. EDL-5, no. 12, pp. 505-507, Dec. 1984.
-
(1984)
IEEE Electron Device Lett.
, Issue.12
, pp. 505-507
-
-
Chan, T.Y.1
Ko, P.K.2
Hu, C.3
-
15
-
-
0025404777
-
d/2 ≥ Vg ≥ Vd) during hot-carrier stressing of n-MOS transistors"
-
Mar
-
d/2 ≥ Vg ≥ Vd) during hot-carrier stressing of n-MOS transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 744-754, Mar. 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, Issue.3
, pp. 744-754
-
-
Doyle, B.1
Bourcerie, M.2
Marchetaux, J.-C.3
Boudou, A.4
-
16
-
-
0028755085
-
"Quasi-breakdown of ultrathin gate oxide under high field stress"
-
S.-H. Lee, B.-J. Cho, J.-C. Kim, and S.-H. Choi, "Quasi-breakdown of ultrathin gate oxide under high field stress," in IEDM Tech. Dig., 1994, pp. 605-607.
-
(1994)
IEDM Tech. Dig.
, pp. 605-607
-
-
Lee, S.-H.1
Cho, B.-J.2
Kim, J.-C.3
Choi, S.-H.4
-
17
-
-
0035340575
-
"Experimental evidence of interface-controlled mechanism of quasi-breakdown in ultrathin gateoxide"
-
May
-
H. Guan, B. J. Cho, M. F. Li, Z. Xu, Y. D. He, and Z. Dong, "Experimental evidence of interface-controlled mechanism of quasi-breakdown in ultrathin gateoxide," IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 1010-1013, May 2001.
-
(2001)
IEEE Trans. Electron Devices
, vol.48
, Issue.5
, pp. 1010-1013
-
-
Guan, H.1
Cho, B.J.2
Li, M.F.3
Xu, Z.4
He, Y.D.5
Dong, Z.6
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