Arithmetic transforms for compositions of sequential and imprecise datapaths

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 7, 2006, Pages 1382-1391

  Radecka, Katarzyna ^a,b   Zilic, Zeljko ^a,b  

^a Dept of Electrical and Computer Engineering   (Canada)

^b MCGILL UNIVERSITY   (Canada)

Author keywords

Arithmetic transform (AT); Hardware verification; Imprecise arithmetic; Sequential circuits

Indexed keywords

DECISION THEORY; FUNCTIONS; INTEGRATED CIRCUITS; MECHANISMS;

ARITHMETIC TRANSFORM (AT); HARDWARE VERIFICATION; IMPRECISE ARITHMETIC;

MATHEMATICAL TRANSFORMATIONS;

EID: 33744725906     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.855935     Document Type: Article

References (24)

1. Z. Zhou and W. Burleson, "Equivalence checking of datapaths based on canonical arithmetic expressions," in Proc. 32nd Design Automation Conf., San Francisco, CA, 1995, pp. 546-551.
2. D. K. Pradhan, S. Askar, and M. Ciesielski, "Mathematical framework for representing discrete functions as word-level polynomials," in Proc. 8th Int. High-Level Design Validation and Test Workshop, San Francisco, CA, 2003, pp. 135-139.
3. Y.-T. Chang and K.-T. Cheng, "Self-referential verification for gate-level implementations of arithmetic circuits," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 23, no. 7, pp. 1102-1112, Jul. 2004.
4. M. A. Thornton, M. D. Miller, and R. Drechsler, Spectral Methods in VLSI CAD. Dordrecht, The Netherlands: Kluwer, 2002.
5. R. P. Bryant and Y. A. Chen, "Verification of arithmetic circuits with binary moment diagrams," in Proc. 32nd Design Automation Conf., San Francisco, CA, 1995, pp. 535-541.
6. K. Hamaguchi, A. Morita, and S. Yajima, "Efficient construction of binary moment diagrams for verification of arithmetic circuits," in Proc. Int. Conf. Computer-Aided Design (ICCAD), San Jose, CA, 1995, pp. 78-82.
7. R. Drechsler, B. Becker, and S. Ruppertz, "The K * BMD: A verification data structure," IEEE Des. Test Comput., vol. 14, no. 2, pp. 51-59, Apr.-Jun. 1997.
8. M. Ciesielski, P. Kalla, Z. Zeng, and B. Rouzeyre, "Taylor expansion diagrams: A compact, canonical representation with applications to symbolic verification," in Proc. Design Automation and Test Eur. (DATE), Paris, France, Mar. 2002, pp. 285-289.
9. G. Fey, R. Drechsler, and M. Ciesielski, "Algorithms for Taylor expansion diagrams," in Proc. 34th Int. Symp. Multiple-Valued Logic, Toronto, ON, Canada, 2004, pp. 235-240.
10. J.-H. R. Jiang and R. K. Brayton, "On the verification of sequential equivalence," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 6, pp. 686-697, Jun. 2003.
11. M. Clark, M. Mulligan, D. Jackson, and D. Linebarger, "Fixed-point modeling in an UWB wireless communication system," in Matlab Dig., 2004, [Online]. Available: www.mathworks.com/company/newsletters/digest/may04/uwb.html
12. J. Smith and G. De Micheli, "Polynomial circuit models for component matching in high-level synthesis," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 6, pp. 783-800, Dec. 2001.
13. D. W. Currie, A. J. Hu, S. Rajan, and M. Fujita, "Automatic formal verification of DSP software," in Proc. 37th ACM/IEEE Design Automation Conf., Los Angeles, CA, 2000, pp. 130-135.
14. K. Radecka and Z. Zilic, "Using arithmetic transform for verification of datapath circuits via error modeling," in Proc. VLSI Test Symp. (VTS), Montreal, QC, Canada, 2000, pp. 271-277.
15. _, "Design verification by test vectors and arithmetic transform universal test set," IEEE Trans. Comput., vol. 53, no. 5, pp. 628-640, May 2004.
16. _, "Arithmetic transforms for verifying compositions of sequential datapaths," in Proc. IEEE Int. Symp. Computer Design, Austin, TX, 2001, pp. 348-358.
17. M. Huhn, K. Schneider, T. Kropf, and G. Logothetis, "Verifying imprecisely working arithmetic circuits," in Proc. Design Automation and Test Eur., Munich, Germany, 1999, pp. 65-69.
18. Z. Zilic and K. Radecka, "On feasible multivariate interpolations over arbitrary fields," in Proc. ACM Int. Symp. Symbolic and Algebraic Computing, Vancouver, BC, Canada, 1999, pp. 67-74.
19. G. De Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.
20. D. Knuth, The Art of Computer Programming. Reading, MA: Addison-Wesley, 1998.
21. D.-U. Lee, W. Luk, J. D. Villasenor, and P. Y. K. Cheung, "A Gaussian noise generator for hardware-based simulations," IEEE Trans. Comput., vol. 53, no. 12, pp. 1523-1534, Dec. 2004.
22. S. A. White, "Applications of distributed arithmetic to digital signal processing: A tutorial," IEEE ASSP Mag., vol. 6, no. 3, pp. 4-19, Jul. 1989.
23. J. Radecki, J. Konrad, and M. Dubois, "The application of two-dimensional finite precision IIR filters to enhanced NTSC encoding," IEEE Trans. Circuits Syst. Video Technol., vol. 6, no. 4, pp. 355-374, Aug. 1992.
24. K. Radecka and Z. Zilic, "Specifying and verifying imprecise circuits by arithmetic transforms," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, San Jose, CA, 2002, pp. 128-131.